ADUC7039BCP6Z-RL Analog Devices Inc, ADUC7039BCP6Z-RL Datasheet - Page 23

• Manufacturer Part Number: ADUC7039BCP6Z-RL
• Description: Flash 64k ARM7 Dual 16-Bit ADC LIN I.C.
• Manufacturer: Analog Devices Inc
• Series: MicroConverter® ADuC7xxxr

Specifications of ADUC7039BCP6Z-RL

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 20.48MHz
• Connectivity: LIN, SPI
• Peripherals: POR, Temp Sensor, WDT
• Number Of I /o: 6
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 18 V
• Data Converters: A/D 2x16b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 115°C
• Package / Case: 32-LFCSP
• Lead Free Status / RoHS Status: Lead free by exemption / RoHS compliant by exemption
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free by exemption / RoHS compliant by exemption

FLASH/EE MEMORY RELIABILITY
The Flash/EE memory array on the part is fully qualified for
two key Flash/EE memory characteristics: Flash/EE memory
cycling endurance and Flash/EE memory data retention.
Endurance quantifies the ability of the Flash/EE memory to be
cycled through many program, read, and erase cycles. A single
endurance cycle is composed of four independent, sequential
events, defined as
•
•
•
•
In reliability qualification, every half-word (16-bit wide) loca-
tion of the three pages (top, middle, and bottom) in the Flash/EE
memory is cycled 10,000 times from 0x0000 to 0xFFFF. As
indicated in Table 1, the Flash/EE memory endurance qualifi-
cation of the part is carried out in accordance with the JEDEC
Retention Lifetime Specification A117. The results allow the
specification of a minimum endurance figure over supply and
temperature of 10,000 cycles.
Retention quantifies the ability of the Flash/EE memory to
retain its programmed data over time. The part is qualified in
accordance with the formal JEDEC Retention Lifetime Specifi-
cation A117 at a specific junction temperature (T
indicated in Table 1. This means that the Flash/EE memory
is guaranteed to retain its data for its fully specified retention
lifetime every time the Flash/EE memory is reprogrammed.
Also, note that retention lifetime, based on an activation energy
of 0.6 eV, derates with T
Initial page erase sequence.
Read/verify sequence.
Byte program sequence.
Second read/verify sequence.
600
450
300
150
0
30
Figure 8. Flash/EE Memory Data Retention
40
JUNCTION TEMPERATURE (°C)
55
J
as shown in Figure 8.
70
85
100
125
135
J
= 85°C) as
150
Rev. B | Page 23 of 92
ADuC7039 KERNEL
The ADuC7039 features an on-chip kernel resident in the
top 2 kB of the Flash/EE code space. After any reset event,
this kernel calculates its own checksum and compares it to the
checksum programmed during production test, to ensure that
the kernel does not contain any error. If an error occurs, the
SYSCHK register contains its default value and user mode is
entered. In normal circumstances, the checksum is written to
the SYSCHK MMR.
System Kernel Checksum
Name:
Address:
Default Value:
Access:
Function:
The kernel then copies the factory calibrated data from the
manufacturing data space into the various on-chip peripherals.
The peripherals calibrated by the kernel are as follows:
•
•
•
•
•
•
Processor registers and user registers that can be modified
by the kernel and differ from their POR default values are as
follows:
•
•
•
•
•
•
•
The ADuC7039 also features an on-chip LIN downloader.
A flow chart of the execution of the kernel is shown in Figure 9.
The current revision of the kernel can be derived from R5, as
described in Table 65.
After any reset, the watchdog timer is disabled once the kernel
code is exited. For the duration of the kernel execution, the
watchdog timer is active with a timeout period of 500 ms. This
ensures that if an error occurs in the kernel, the ADuC7039
automatically resets. If LIN download mode is entered, the
watchdog is periodically refreshed.
Precision oscillator
Low power oscillator
REG_AVDD/REG_DVDD
Voltage reference
Current ADC (offset and gain)
Voltage/temperature ADC (offset and gain)
R0 to R15
GP0CON
SYSCHK
FEEADR/FEEDAT/FEECON/FEESIG
HVDAT/HVCON
HVCFG
T2LD
SYSCHK
0x00000000 (updated by kernel at power-on)
Read/write
At power-on, this 32-bit register holds the
kernel checksum.
0xFFFF0244
ADuC7039