DJLXT384LE Intel, DJLXT384LE Datasheet - Page 109

• Manufacturer Part Number: DJLXT384LE
• Manufacturer: Intel

Specifications of DJLXT384LE

• Lead Free Status / RoHS Status: Not Compliant

11.2
11.2.1
Document Number: 248994
Revision Number: 005
Revision Date: November 28, 2005
Table 67. Intel
Host Processor Mode - Parallel Interface Timing
This sections gives timing characteristics and timing diagrams for both Intel
Motorola processors.
Intel
Table 67
Address setup time to latch
Valid address latch pulse width
Latch active to active read setup time
Chip select setup time to active read
Chip select hold time from inactive read
Address hold time from inactive ALE
Active read to data valid delay time
Address setup time to RD inactive
Address hold time from RD inactive
Inactive read to data high-impedance tristate delay
time
Valid read signal pulse width
Inactive read to inactive INT delay time
Active chip select to RDY delay time
Active ready low time
Inactive ready to high-impedance tristate delay time
1. Minimum and maximum values are at 25 C° and are for design aid only, not guaranteed, and not subject
to production testing.
®
®
Processor - Read Timing Characteristics
Processor - Parallel Interface Timing
lists read timing characteristics for the Intel
Parameter
Intel
®
LXT384 Octal T1/E1/J1 S/H PCM Transceiver with JA
®
t
t
t
t
t
Sym.
t
t
SCSR
HSCR
HALR
t
t
t
t
t
DRDY
VRDY
RDYZ
SALR
t
t
PRD
HAR
SAR
ZRD
VRD
processor.
t
SLR
INT
VL
Min.
10
30
10
10
60
0
0
5
1
5
3
–
0
–
–
1
Max.
50
35
10
12
40
–
–
–
–
–
–
–
–
3
1
®
processors and
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
C
pF on D7:0.
All other
outputs are
loaded with
50 pF.
Conditions
Load
Test
= 100
109