DJLXT384LE Intel, DJLXT384LE Datasheet - Page 80
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DJLXT384LE
Manufacturer Part Number
DJLXT384LE
Description
Manufacturer
Intel
Datasheet
1.DJLXT384LE.pdf
(140 pages)
Specifications of DJLXT384LE
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Table 38. Reset Register, RES - 0Ah
®
LXT384 Octal T1/E1/J1 S/H PCM Transceiver with JA
Bit
7:0
RES7:0
Name
Reset.
The RES7:0 bits are used to set all LXT384 Transceiver registers to their
default values.
For details on non-multiplexed and multiplexed modes, see
Processor
• Except when using an Intel
• When using Intel
to this field initiates a 1-microsecond software reset cycle.
extend the software reset cycle time to 2 microseconds. (For more
information on the software reset cycle when using an Intel
non-multiplexed mode, see
Interface”.)
Modes”.
®
processor in a non-multiplexed mode, to use this field
®
Section 7.4.1, “Host Processor Mode - Parallel
Description
processor in a non-multiplexed mode, writing
Revision Date: November 28, 2005
Section 7.4, “Host
®
processor in a
Document Number: 248994
Revision Number: 005
R/W
R/W
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