DJLXT384LE Intel, DJLXT384LE Datasheet - Page 90

• Manufacturer Part Number: DJLXT384LE
• Manufacturer: Intel

Specifications of DJLXT384LE

• Lead Free Status / RoHS Status: Not Compliant

Intel
90
Table 51. Boundary Scan Register (BSR) (Sheet 2 of 4)
®
LXT384 Octal T1/E1/J1 S/H PCM Transceiver with JA
Bit #
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
RNEG1
RNEG0
RNEG3
RNEG2
TPOS0
TNEG0
RPOS0
RPOS3
TNEG3
TPOS3
RPOS2
TNEG2
TPOS2
TCLK0
RCLK0
RCLK3
TCLK3
RCLK2
TCLK2
Signal
LOS1
LOS0
LOS3
LOS2
MUX
ACK
N/A
N/A
N/A
N/A
N/A
Pin
INT
I/O Type
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
-
I
I
I
-
I
-
I
I
I
-
I
I
I
-
SDOACKENB
Symbol
RNEG1
TNEG0
RPOS0
RNEG0
RNEG3
RPOS3
TNEG3
RNEG2
RPOS2
TNEG2
TPOS0
RCLK0
RCLK3
TPOS3
RCLK2
TPOS2
TCLK0
TCLK3
TCLK2
LOS1
LOS0
LOS3
LOS2
HIZ1
HIZ0
MUX
HIZ3
HIZ2
ACK
INT
Bit
HIZ1 controls the RPOS1, RNEG1 and RCLK1 pins. Setting
HIZ1 to “0” enables output on the pins. Setting HIZ1 to “1”
tristates the pins.
HIZ0 controls the RPOS0, RNEG0 and RCLK0 pins. Setting
HIZ0 to “0” enables output on the pins. Setting HIZ0 to “1”
tristates the pins.
HIZ3 controls the RPOS3, RNEG3 and RCLK3 pins. Setting
HIZ3 to “0” enables output on the pins. Setting HIZ3 to “1”
tristates the pins.
HIZ2 controls the RPOS2, RNEG2 and RCLK2 pins. Setting
HIZ2 to “0” enables output on the pins. Setting HIZ2 to “1”
tristates the pins.
SDOACKENB controls the ACK pin. Setting SDOACKEN to
“0” enables output on ACK pin. Setting SDOACKEN to “1”
tristates the pin.
Comments
Revision Date: November 28, 2005
Document Number: 248994
Revision Number: 005