DJLXT384LE Intel, DJLXT384LE Datasheet - Page 73

• Manufacturer Part Number: DJLXT384LE
• Manufacturer: Intel

Specifications of DJLXT384LE

• Lead Free Status / RoHS Status: Not Compliant

7.4.2
Document Number: 248994
Revision Number: 005
Revision Date: November 28, 2005
Figure 14. Host Processor Mode - Serial Interface Read Timing
SCLK
SDO
CS
SDI
R/W = 1: Read operation
R/W = 0: Write operation (SDO remains high impedance)
R/W
Host Processor Mode - Serial Interface
A Host Processor mode with a serial interface consisting of the CS, SCLK, SDI, and SDO pins is
selected by connecting the MODE pin to a voltage that is equal to 1/2 VCC (which can be
accomplished by connecting one 10k Ω resistor to VCC and a second 10k Ω resistor to ground).
Figure 14
accessible through a 16-bit word consisting of the following:
•
•
An 8-bit Address/Command byte.
A subsequent 8-bit Data byte. (Depending on the R/W state, the D0-D7 values are valid on
either SDI or SDO, but never are the D0-D7 values valid on both SDI and SDO.)
A1
— The signal on the R/W pin determines whether a read or a write operation occurs.
— The signals on pins A1-A5 go to an address decoder that decodes an address. (The address
— When R/W = 0, D0-D7 on SDO are don’t cares. The D0-D7 values on SDI are active,
— When R/W = 1, the D0-D7 values on SDO are active, with valid data that the LXT384
decoder ignores signals on the A6 and A7 pins.)
with valid data being written to the LXT384 Transceiver.
Transceiver writes to the host processor. The D0-D7 values on SDI are don’t cares.
Address / Command Byte
shows timing for the host processor interface when it is in serial mode. Registers are
A2
High Impedance
A3
A4
A5
(Don't
care)
A6
Intel
(Don't
care)
A7
®
LXT384 Octal T1/E1/J1 S/H PCM Transceiver with JA
D0
D0
D1
D1
Input (Write) Data Byte
D2
D2
Output (Read) Data Byte
D3
D3
D4
D4
D5
D5
D6
D6
D7
D7
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