DJLXT384LE Intel, DJLXT384LE Datasheet - Page 41
DJLXT384LE
Manufacturer Part Number
DJLXT384LE
Description
Manufacturer
Intel
Datasheet
1.DJLXT384LE.pdf
(140 pages)
Specifications of DJLXT384LE
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5.7
Document Number: 248994
Revision Number: 005
Revision Date: November 28, 2005
Table 13. Signal Loss and Line-Code-Violation Signals
Signal Loss and Line-Code-Violation Signals
Table 13
A4
A3
A2
A1
A0
BPV7:0
CLKE
LOS7
LOS6
LOS5
LOS4
LOS3
LOS2
LOS1
LOS0
RCLK7:0
1. DI: Digital Input. DO: Digital Output.
Signal
Name
lists and the signal loss and line-code violation signals for the LXT384 Transceiver.
QFP
140
106
Pin
113
12
13
14
15
16
68
75
35
42
3
PBGA
Ball
E11
K11
K12
E12
G3
F4
F3
F2
F1
E4
E3
K3
K4
I/O
DO
DI
1
Intel
Performance Monitoring Input.
When the LXT384 Transceiver is in the:
Bipolar Violation Detect Output 7:0.
For information on the BPV signals, see
Mapper
Clock Edge Select Input.
For information on how CLKE is used for clock and data recovery,
see
Loss of Signal Output.
LOS is:
NOTE: When a loss-of-signal condition is cleared, LOS returns to
Receive Clock Output 7:0.
For information on how RCLK is used for clock and data recovery,
see
• Hardware mode, the A3:0 pins make the performance-
• Host Processor mode:
• Low when a loss-of-signal condition is cleared (incoming signal
• High (indicating a loss of signal), when there is no incoming
®
monitoring selections shown in
to ground.
• These pins no longer control the monitoring function. Instead,
• For information on how to control performance monitoring,
Section 5.5, “Clocks and Clock-Related
with normal levels, being processed through the transceiver).
signal (sequence of marks for a specified time interval).
Section 5.3, “Framer/Mapper
LXT384 Octal T1/E1/J1 S/H PCM Transceiver with JA
in non-multiplexed host mode, these pins function as non-
multiplexed address pins (see
Standard Bus and Interface
see
on page
Signals”.
low when an incoming signal has a sufficient number of
transitions in a specified time interval. (For details, see
Section 6.3.3, “Receiver Loss-Of-Signal
Table 39, “Performance-Monitoring Register, MON - 0Bh”
81.
Signal Description
Signals”.
Signals”).
Table
Section 5.2, “Microprocessor-
Section 5.3, “Framer/
14. A4 must be connected
Signals”.
Detector”.)
41
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