DJLXT384LE Intel, DJLXT384LE Datasheet - Page 83

• Manufacturer Part Number: DJLXT384LE
• Manufacturer: Intel

Specifications of DJLXT384LE

• Lead Free Status / RoHS Status: Not Compliant

Document Number: 248994
Revision Number: 005
Revision Date: November 28, 2005
Table 43. Global Control Register, GCR - 0Fh
1. On power-on reset, the register is set to ‘0’.
Bit
1:0
7
6
5
4
3
2
JASEL1:0
RAISEN
CODEN
FIFO64
Name
JACF
CDIS
-
Reserved.
Receive Alarm Indication Signal Enable.
This bit controls automatic AIS insertion in the receive path when LOS occurs.
NOTE: This feature is not available in data-recovery mode (that is, when
Circuit Disable.
This bit enables/disables the short-circuit protection feature for the transmitters.
Code Enable.
This bit selects one of two available zero-suppression codes. Zero suppression
operations are available only with unipolar I/O.
First-In First-Out 64-Bit Select.
This bit determines the jitter attenuator FIFO depth as follows:
Jitter Attenuator Corner Frequency.
This bit determines the jitter attenuator low-limit 3-dB corner frequency. For
more information, see
Jitter Attenuator Select.
These bits determine the jitter attenuator position as follows:
• 0 = Receive path AIS insertion is disabled on LOS.
• 1 = Receive path AIS insertion is enabled on LOS, and the effective output
• 0 = Enable
• 1 = Disable
• 0 = High-Density Bipolar three (HDB3) for E1 or B8ZS for T1
• 1 = Alternate Mark Inversion, or ‘AMI’. The following figure shows AMI
• 0 = Jitter attenuator FIFO is 32 bits deep.
• 1 = Jitter attenuator FIFO is 64 bits deep.
JASEL1
appears on RPOS/RNEG.
coding that is 1:1 (or ‘50%’), indicating that for every one bit sit to a ‘1’,
there is a corresponding ‘0’ logic state.
x
0
1
MCLK is high). When changing the value of the RAISEN bit, disable
AIS interrupts to prevent inadvertent interrupts.
TRING
TTIP
JASEL0
Intel
0
1
1
Bit Cell
Chapter 14.0, “Jitter
®
1
LXT384 Octal T1/E1/J1 S/H PCM Transceiver with JA
Jitter attenuator is disabled.
Jitter attenuator position is the transmit path.
Jitter attenuator position is the receive path.
Description
Jitter Attenuator Position
0
Performance”.
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
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