DJLXT384LE Intel, DJLXT384LE Datasheet - Page 82

• Manufacturer Part Number: DJLXT384LE
• Manufacturer: Intel

Specifications of DJLXT384LE

• Lead Free Status / RoHS Status: Not Compliant

Intel
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Table 40. Digital Loopback Register, DL - 0Ch
Table 41. LOS/AIS Criteria Selection Register, LACS - 0Dh
Table 42. Automatic TAOS Select Register, ATS - 0Eh
®
LXT384 Octal T1/E1/J1 S/H PCM Transceiver with JA
Bit
7:0
Bit
7:0
Bit
7:0
LACS7:0
ATS7:0
Name
Name
Name
DL7:0
Digital Loopback.
During digital loopback, LOS and TAOS stay active and independent of TCLK,
while data received on TPOS, TNEG, and CKLK loop back to RPOS, RNEG,
and RCLK.
Loss of Signal / Alarm Indication Signal Selection Criteria.
Automatic Transmit-All-Ones Select.
NOTE: This register does not work during either data-recovery mode or line-
• On power-up, the DL7:0 bits are cleared to ‘0’, and all digital loopback
• Setting a DL bit to ‘1’ enables digital loopback for its corresponding
• At power-up, all LACS7:0 bits are cleared to ‘0’.
• After power-up, programming an LACS bit to:
• In T1 mode, this register is “Don’t Care.” The LXT384 Transceiver uses
• On power-on, all ATS7:0 bits are cleared to ‘0’.
• When this field is set to ‘1’, then when there is an LOS condition, TAOS
channels are disabled.
transceiver.
• ‘0’ selects the ITU G.775 mode [for LOS, AIS, and remote detect
• ‘1’ selects the ETSI 300 233 LOS and AIS detection mode for the
T1.231 compliant LOS/AIS detection.
can be generated automatically.
indication (RDI)] for its corresponding receiver.
corresponding receiver.
driver mode (that is, when both MCLK = High and TCLK = High).
Description
Description
Description
Revision Date: November 28, 2005
Document Number: 248994
Revision Number: 005
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