DJLXT384LE Intel, DJLXT384LE Datasheet - Page 69
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DJLXT384LE
Manufacturer Part Number
DJLXT384LE
Description
Manufacturer
Intel
Datasheet
1.DJLXT384LE.pdf
(140 pages)
Specifications of DJLXT384LE
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7.0
7.1
7.2
Document Number: 248994
Revision Number: 005
Revision Date: November 28, 2005
Operating Mode Summary
This section discusses the following operating modes:
Interfacing with 5V Logic
The LXT384 Transceiver can interface directly with 5V TTL family devices. The internal input
pads can tolerate 5V outputs from TTL and CMOS family devices.
Hardware Mode
The Hardware mode is selected when the MODE pin is connected low, which disables the Host
Processor interface. In the Hardware mode, the Host Processor interface pins have different
functions, in that they can be hard-wired to control the LXT384 Transceiver for various operation
modes and to report on the status of operations.
•
•
•
•
•
Section 7.1, “Interfacing with 5V Logic”
Section 7.2, “Hardware Mode”
Section 7.3, “Hardware Mode Settings”
Section 7.4, “Host Processor Modes”
Section 7.5, “Interrupt Handling”
Intel
®
LXT384 Octal T1/E1/J1 S/H PCM Transceiver with JA
69
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