DJLXT384LE Intel, DJLXT384LE Datasheet - Page 39

• Manufacturer Part Number: DJLXT384LE
• Manufacturer: Intel

Specifications of DJLXT384LE

• Lead Free Status / RoHS Status: Not Compliant

5.6
Document Number: 248994
Revision Number: 005
Revision Date: November 28, 2005
Table 12. Configuration and Mode-Select Signals (Sheet 1 of 2)
Configuration and Mode-Select Signals
Table 12
multi-function pins, the pin name in
CODEN
MOT
CODEN /
/ MOT
CS
CS /
1. DI: Digital Input
/ JASEL
Signal
Name
JASEL
/ INTL /
lists and describes the LXT384 Transceiver configuration and mode-select signals. For
INTL
QFP
Pin
88
88
87
87
PBGA
Ball
H12
H12
J11
J11
I/O
DI
DI
DI
DI
1
Intel
blue bold
Codec Enable Select Input.
When the LXT384 Transceiver is in the Hardware mode, CODEN
determines the line encoder/decoder selection when in unipolar
mode. When CODEN is:
NOTE: In the host processor mode, the encoding/decoding type
For other pin functions, see INTL/MOT.
Host Processor Select Input.
When the LXT384 Transceiver is in the host processor mode and
this signal is:
For other pin functions, see CODEN.
Chip Select Input.
In Host Mode, this active Low input is used to access the serial/
parallel interface. For each read or write operation, CS must
transition from High to Low, and remain Low.
For information on the CS signal, see
“Microprocessor-Standard Bus and Interface
Jitter Attenuator Select Input.
When the LXT384 Transceiver is in the Hardware mode, JASEL
determines the jitter attenuator (JA) position, as listed in the
following table.
For other pin functions, see CS in
Standard Bus and Interface
®
• Low, it enables an HDB3 encoder/decoder for E1 or a B8ZS
• High, it enables an AMI encoder/decoder (transparent mode).
• high, the host processor interface is configured for Intel
• low, the host processor interface is configured for Motorola
High impedance
LXT384 Octal T1/E1/J1 S/H PCM Transceiver with JA
encoder/decoder for T1.
microcontrollers.
microcontrollers.
JASEL
print indicates the signal being discussed.
is determined by the CODEN bit. (For CODEN bit details,
see
High
Low
Chapter 8.0,
Signal Description
JA is disabled
Transmit path
Receive path
JA Position
“Registers”.)
Signals”.
Section 5.2, “Microprocessor-
Section 5.2,
Signals”.
®
39