DJLXT384LE Intel, DJLXT384LE Datasheet - Page 84

• Manufacturer Part Number: DJLXT384LE
• Manufacturer: Intel

Specifications of DJLXT384LE

• Lead Free Status / RoHS Status: Not Compliant

Intel
84
Table 44. Pulse Shaping Indirect Address Register, PSIAD (10h)
Table 45. Pulse Shaping Data Register, PSDAT (11h) for Intel
Table 46. Output Enable Register, OER - 12h
®
LXT384 Octal T1/E1/J1 S/H PCM Transceiver with JA
3 - 7
3 - 7
Bit
0-2
0-2
1. On power-on reset the register is set to “0”.
Bit
1. On power-on reset the register is set to “0”.
2. Maximum cable loss at 772 KHz.
3. When reading LEN, bit values appear inverted.
Bit
7:0
1
LENAD 0-2
LEN 0-2
Name
Name
Name
OE7:0
-
-
1
Output Enable.
• On power-up, all OE7:0 bits are cleared to ‘0’.
• When an OE bit is set to ‘1’, the output driver of its corresponding
The three bit value written to these bits determine the channel to be addressed. Data
can be read from (written to) the Pulse Shaping Data Register (PSDAT).
LENAD 0-2
Reserved.
LEN0-2 determine the operation mode of the LXT384 Transceiver: T1 or E1. In
addition, for T1 operation, LEN2-0 set the pulse shaping to meet the T1.102 pulse
template at the DSX-1 cross-connect point for various cable lengths:
Reserved.
LEN2
0h
1h
2h
3h
transmitter goes into a high-impedance tristate.
0
1
1
1
1
0
LEN1
1
0
0
1
1
0
Channel
LEN0
0
1
2
3
1
0
1
0
1
0
0 - 133 ft. ABAM
133 - 266 ft. ABAM
266 - 399 ft. ABAM
399 - 533 ft. ABAM
533 - 655 ft. ABAM
E1 G.703, 75Ω coaxial cable and 120Ω
twisted pair cable.
Line Length
Description
LENAD 0-2
Function
Function
4h
5h
6h
7h
®
LXT384 Transceiver
Cable Loss
Channel
0.6 dB
1.2 dB
1.8 dB
2.4 dB
3.0 dB
Revision Date: November 28, 2005
4
5
6
7
Document Number: 248994
2
Revision Number: 005
Operation
Mode
T1
E1
R/W
R/W