DJLXT384LE Intel, DJLXT384LE Datasheet - Page 75

• Manufacturer Part Number: DJLXT384LE
• Manufacturer: Intel

Specifications of DJLXT384LE

• Lead Free Status / RoHS Status: Not Compliant

8.0
8.1
Document Number: 248994
Revision Number: 005
Revision Date: November 28, 2005
Table 25. Intel
Registers
This chapter discusses the LXT384 Transceiver registers.
Register Summary
Table 25
Address
(Hex)
0A
0B
0C
0D
0E
0F
00
01
02
03
04
05
06
07
08
09
10
11
12
13
14
15
®
LXT384 Transceiver Register Summary
lists LXT384 Transceiver registers by the hex address of each.
Mnemonic
ALOOP
RLOOP
TAOS
LACS
AISIE
AISIS
MON
GCR
OER
LOS
RES
ATS
AIS
LIE
LIS
DL
ID
-
-
-
-
-
Table 28, “ID Register, ID - 00h”
Table 29, “Analog Loopback Register, ALOOP - 01h”
Table 30, “Remote Loopback Register, RLOOP - 02h”
Table 31, “TAOS Enable Register, TAOS - 03h”
Table 32, “LOS Status Monitor Register, LOS - 04h”
Reserved
Table 34, “LOS Interrupt Enable Register, LIE - 06h”
Reserved
Table 36, “LOS Interrupt Status Register, LIS - 08h”
Reserved
Table 38, “Reset Register, RES - 0Ah”
Table 39, “Performance-Monitoring Register, MON - 0Bh”
Table 40, “Digital Loopback Register, DL - 0Ch”
Table 41, “LOS/AIS Criteria Selection Register, LACS - 0Dh”
Table 42, “Automatic TAOS Select Register, ATS - 0Eh”
Table 43, “Global Control Register, GCR - 0Fh”
Reserved
Reserved
Table 46, “Output Enable Register, OER - 12h”
Table 47, “AIS Status Monitor Register, AIS - 13h”
Table 48, “AIS Interrupt Enable Register, AISIE - 14h”
Table 49, “AIS Interrupt Status Register, AISIS - 15h”
Intel
®
LXT384 Octal T1/E1/J1 S/H PCM Transceiver with JA
Cross-Reference
75