DJLXT384LE Intel, DJLXT384LE Datasheet - Page 57

• Manufacturer Part Number: DJLXT384LE
• Manufacturer: Intel

Specifications of DJLXT384LE

• Lead Free Status / RoHS Status: Not Compliant

6.5
Document Number: 248994
Revision Number: 005
Revision Date: November 28, 2005
Line-Interface Protection
Figure 6
Intel
and tolerances of devices used with line-interface protection circuitry, see
“Line-Interface-Unit Circuit
For some power-up operations, on rare occasions there is no activity for several seconds on all of
the following transmit-side pins: TPOS, TNEG, TCLK, and MCLK. If this lack of activity occurs
for a period of several seconds, then it can cause transmitter outputs to remain in their last-known
logic state. If the transmitter outputs are in static mode. As a result, then the transformer output
appears as a short circuit to this static DC voltage.
In the worst case of inactivity, one of the transmitter outputs is high while other transmitter outputs
are low. In this case, outputs TTIP and TRING would draw excessive current through the
transformer primary windings and the LXT384 Transceiver can overheat. To manage this type of
power-up operation, do only one of the following:
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Receive side. Two 1kΩ resistors protect the receiver against current surges that can couple
into the LXT384 Transceiver. Due to the high receiver impedance (typically 70 kΩ), these
resistors do not affect the receiver sensitivity.
Transmit side. Resistors R
surges. To protect the LXT384 Transceiver output driver from surge currents in excess of 100
mA, a transient voltage suppressor TVS1 (such as Teccor P0080S) is required.
Set OE low until normal operations return.
Set TCLK low until normal operations return.
Set TNEG low until normal operations return.
Set TPOS low until normal operations return.
Provide MCLK with a frequency from 10 kHz to 10 MHz until normal operations return.
Provide TCLK with a frequency from 100 kHz to 10 MHz until normal operations return.
Toggle TNEG with a clock from 100 kHz to 10 MHz until normal operations return.
Toggle TPOS with a clock from 100 kHz to 10 MHz until normal operations return.
As shown in
resistors.
strongly recommends these line-interface protection elements.) For the appropriate values
shows circuitry for line-interface protection. (While not mandatory for normal operation,
Figure
6, add a single 0.47 uF capacitor in series with one of the R
Specifications”.
T
and Schottky diodes D1-4 protect the output drivers from line
Intel
®
LXT384 Octal T1/E1/J1 S/H PCM Transceiver with JA
Table 73
in
T
Chapter 12.0,
output
57