DJLXT384LE Intel, DJLXT384LE Datasheet - Page 47

• Manufacturer Part Number: DJLXT384LE
• Manufacturer: Intel

Specifications of DJLXT384LE

• Lead Free Status / RoHS Status: Not Compliant

6.1
6.2
Document Number: 248994
Revision Number: 005
Revision Date: November 28, 2005
Note: MCLK should be true to the recovered clock of the incoming data. It should be only
Note: For more information related to reset, see
Functional Overview
The LXT384 Transceiver is a fully integrated octal line interface unit designed for T1 1.544 Mbps
and 2.048 Mbps (E1) short-haul applications. (For a block diagram, see
The LXT384 Transceiver can be controlled either by a ‘Hardware mode’ that uses hard-wired pins
or by a ‘Host Processor mode’, which uses either a serial or parallel host processor interface that is
controlled in software. (For more information on selecting an operating mode, see
Section 4.1, “Operating Mode Multi-Function
Each transceiver front end interfaces with four lines: one pair of two lines for transmit, and one pair
of two lines for receive. These two pairs make up a digital data loop for full-duplex transmission.
The TCLK pin provides the transmitter timing reference, and the MCLK pin provides the receiver
reference clock. The LXT384 Transceiver is designed to operate without any reference clock when
it is used as an analog front end (that is, for data recovery in the receiver path and as a line driver in
the transmit path). MCLK is mandatory if on-chip clock recovery is required.
plesiochronous to MCLK.
All eight clock-recovery circuits share the same reference clock defined by the MCLK input signal.
(For details on MCLK, see
Initialization and Reset
Initialization for the LXT384 Transceiver occurs as follows:
Interface”.
1. During power-up, the LXT384 Transceiver is in an unknown state until the power supply
2. A write to the reset register (RES,
reaches approximately 60% of VCC. Also during power-up, an initial reset sets all registers to
their default values and resets the status and state machines for the LOS detector circuit.
(Between 50 and 70% of VCC, the LXT384 Transceiver is in a critical zone. For more
information about this critical zone, see the application note on slow power-up rise time,
referenced in
LXT384 Transceiver registers to their default values. When the reset cycle occurs:
a. In the Intel
b. In all other modes, the reset cycle is 1 microsecond long.
Section 1.3, “Related
®
processor non-multiplexed mode, the reset cycle is 2 microseconds long.
Table 11
Intel
in
Table
Section 5.5, “Clocks and Clock-Related
Documents”.)
®
Section 7.4.1, “Host Processor Mode - Parallel
LXT384 Octal T1/E1/J1 S/H PCM Transceiver with JA
38) initiates a reset cycle that results in setting all
Pins”.)
Figure
1.)
Signals”.)
Table 3
in
47