DJLXT384LE Intel, DJLXT384LE Datasheet - Page 79

• Manufacturer Part Number: DJLXT384LE
• Manufacturer: Intel

Specifications of DJLXT384LE

• Lead Free Status / RoHS Status: Not Compliant

Document Number: 248994
Revision Number: 005
Revision Date: November 28, 2005
Table 32. LOS Status Monitor Register, LOS - 04h
Table 33. DFM Status Monitor Register, DFM (05h) for Intel
Table 34. LOS Interrupt Enable Register, LIE - 06h
Table 35. DFM Interrupt Enable Register, DIE (07h) for Intel
Table 36. LOS Interrupt Status Register, LIS - 08h
Table 37. DFM Interrupt Status Register, DIS (09h) for Intel
7-0
7-0
7-0
Bit
Bit
Bit
1. On power-up all the register bits are set to “0”. All DFM interrupts are cleared by a single read operation.
1. On power-up all the register bits are set to “0” and all interrupts are disabled.
1. On power up all register bits are set to “0”.
Bit
7:0
Bit
7:0
Bit
7:0
DFM7-DFM0
DIE7-DIE0
DIS7-DIS0
LOS7:0
Name
Name
Name
LIE7:0
LIS7:0
Name
Name
Name
Loss Of Signal Status Monitor.
Loss Of Signal Interrupt Enable.
Loss Of Signal Interrupt Status.
Respective bit(s) are set to “1” every time the short circuit monitor detects a valid
secondary output driver short circuit condition in transceivers 7-0. Note: DFM is
available only in configurations with no transmit series resistors (T1 mode with
TVCC=3.3V).
Transceiver 7-0 DFM interrupts are enabled by writing a “1” to the respective bit.
These bits are set to “1” every time a DFM status change has occurred since the last
cleared interrupt in transceivers 7-0 respectively.
• On power-up, the LOS7:0 bits are cleared to ‘0’.
• All LOS interrupts are cleared by a single read operation.
• Each time the LOS detector detects a valid loss-of-signal condition on a
• On power-up, the LIE7:0 bits are cleared to ‘0’ and all LOS interrupts are
• Writing a ‘1’ to an LIE bit enables an LOS interrupt for its corresponding
• On power-up, the LIS7:0 bits are cleared to ‘0’.
• After an LOS interrupt is cleared, then each time there is a change in the
receiver, its corresponding LOS bit is set to ‘1’.
disabled.
receiver.
LOS status of a receiver, the corresponding LIS bit is set to ‘1’.
Intel
®
LXT384 Octal T1/E1/J1 S/H PCM Transceiver with JA
Description
Description
Description
Function
Function
Function
®
®
®
LXT384 Transceiver
LXT384 Transceiver
LXT384 Transceiver
1
1
1
R/W
R/W
R/W
R/W
R
R
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