DJLXT384LE Intel, DJLXT384LE Datasheet - Page 94

• Manufacturer Part Number: DJLXT384LE
• Manufacturer: Intel

Specifications of DJLXT384LE

• Lead Free Status / RoHS Status: Not Compliant

Intel
9.4.2
9.4.3
9.4.4
94
Table 52. Analog Port Scan Register (ASR)
Table 53. Device Identification Register (IDR)
®
LXT384 Octal T1/E1/J1 S/H PCM Transceiver with JA
Analog Port Scan Register (ASR)
The ASR is a 5 bit shift register used to control the analog test port at pins AT1, AT2. When the
INTEST_ANALOG instruction is selected, TDI connects to the ASR input and TDO connects to
the ASR output. After 5 TCK rising edges, a 5 bit control code is loaded into the ASR. Data into
the ASR is shifted in LSB first.
Table 52
Device Identification Register (IDR)
The IDR register provides access to the manufacturer number, part number and the LXT384
Transceiver revision. The register is arranged per IEEE 1149.1 and is represented in
into the IDR is shifted in LSB first.
Bypass Register (BYR)
The Bypass Register is a 1 bit register that allows direct connection between the TDI input and the
TDO output.
ASR Control Code
11010
11001
11000
10110
10101
10100
10011
10010
10001
10000
31 - 28
27 - 12
11110
11101
11100
11011
10111
11111
11 - 1
Bit #
shows the 16 possible control codes and the corresponding operation on the analog port.
0
AT1 Forces Voltage To:
Revision number
Part number
Manufacturer number
Set to “1”
RTIP0
RTIP1
RTIP2
RTIP3
RTIP4
RTIP5
RTIP6
RTIP7
TTIP0
TTIP1
TTIP2
TTIP3
TTIP4
TTIP5
TTIP6
TTIP7
Comments
AT2 Senses Voltage From:
RRING0
RRING1
RRING2
RRING3
RRING4
RRING5
RRING6
RRING7
TRING0
TRING1
TRING2
TRING3
TRING4
TRING5
TRING6
TRING7
Revision Date: November 28, 2005
Document Number: 248994
Revision Number: 005
Table
53. Data