DJLXT384LE Intel, DJLXT384LE Datasheet - Page 112

• Manufacturer Part Number: DJLXT384LE
• Manufacturer: Intel

Specifications of DJLXT384LE

• Lead Free Status / RoHS Status: Not Compliant

Intel
112
Table 68. Intel
®
LXT384 Octal T1/E1/J1 S/H PCM Transceiver with JA
Table 68
Address setup time to latch
Valid address latch pulse width
Latch active to active write setup time
Chip select setup time to active write
Chip select hold time from inactive write
Address hold time from inactive ALE
Data valid to write active setup time
Data hold time to active write
Address setup time to WR inactive
Address hold time from WR inactive
Valid write signal pulse width
Inactive write to inactive INT delay time
Chip select to RDY delay time
Low time for active RDY
Delay time between inactive RDY to high-
impedance tristate
1. Minimum and maximum values are at 25 C° and are for design aid only, not guaranteed, and not subject to
2. Timing parameters do not apply for Reset Register 0Ah. For details, see
production testing.
Mode - Parallel
®
Processor - Write Timing Characteristics
lists write timing characteristics for the Intel
2
Interface”.
Parameter
2
t
t
t
t
t
t
t
Sym.
HCSW
t
SCSW
HALW
t
t
t
t
DRDY
SALW
t
VRDY
RDYZ
SDW
HDW
HAW
VWR
t
SLW
SAW
t
INT
VL
®
processor.
Min.
10
30
10
40
30
60
0
0
5
2
6
–
0
–
–
1
Max.
Section 7.4.1, “Host Processor
10
12
40
–
–
–
–
–
–
–
–
–
–
3
1
Revision Date: November 28, 2005
Unit
Document Number: 248994
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Revision Number: 005
C
pF on D7:0.
All other
outputs are
loaded with
50 pF.
Conditions
Load
Test
= 100