EP4CE55F23C8N Altera, EP4CE55F23C8N Datasheet - Page 133

• Manufacturer Part Number: EP4CE55F23C8N
• Description: IC CYCLONE IV FPGA 55K 484FBGA
• Manufacturer: Altera
• Series: CYCLONE® IV Er

Specifications of EP4CE55F23C8N

• Number Of Logic Elements/cells: 55856
• Number Of Labs/clbs: 3491
• Total Ram Bits: 2340000
• Number Of I /o: 324
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Family Name: Cyclone IV
• Number Of Logic Blocks/elements: 55856
• # I/os (max): 324
• Logic Cells: 55856
• Ram Bits: 2396160
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 6: I/O Features in Cyclone IV Devices
High-Speed I/O Interface
Table 6–7. Differential I/O Standards Supported in Cyclone IV GX I/O Banks
© December 2010 Altera Corporation
LVDS
RSDS
mini-LVDS
PPDS
BLVDS
LVPECL
Differential SSTL-2
Differential SSTL-18
Differential HSTL-18
Differential HSTL-15
Differential HSTL-12
Notes to
(1) Transmitter and Receiver f
(2) The LVPECL I/O standard is only supported on dedicated clock input pins.
(3) The differential SSTL-2, SSTL-18, HSTL-18, HSTL-15, and HSTL-12 I/O standards are only supported on clock input pins and PLL output clock
Differential I/O Standards
pins. PLL output clock pins do not support Class II interface type of differential SSTL-18, HSTL-18, HSTL-15, and HSTL-12 I/O standards.
(1)
Table
(2)
6–7:
(3)
(3)
(3)
(3)
(3)
You can use I/O pins and internal logic to implement a high-speed differential
interface in Cyclone IV devices. Cyclone IV devices do not contain dedicated
serialization or deserialization circuitry. Therefore, shift registers, internal
phase-locked loops (PLLs), and I/O cells are used to perform serial-to-parallel
conversions on incoming data and parallel-to-serial conversion on outgoing data. The
differential interface data serializers and deserializers (SERDES) are automatically
constructed in the core logic elements (LEs) with the Quartus II software ALTLVDS
megafunction.
MAX
depend on system topology and performance requirement.
I/O Bank Location
3,4,5,6,7,8
3,4,5,6,7,8
3,4,5,6,7,8
3,4,5,6,7,8
3,4,5,6,7,8
3,4,5,6,7,8
3,4,5,6,7,8
3,4,5,6,7,8
3,4,5,6,7,8
3,4,5,6,7,8
4,5,6,7,8
3,4,7,8
5,6
5,6
5,6
5,6
External Resistor
Three Resistors
Three Resistors
Three Resistors
Three Resistors
Single Resistor
Single Resistor
Not Required
Not Required
Not Required
Not Required
Transmitter
Network at
—
—
—
—
—
—
Transmitter (TX)
Cyclone IV Device Handbook, Volume 1
v
v
v
v
v
—
v
v
v
v
v
Receiver (RX)
v
v
v
v
v
v
v
v
—
—
—
6–25