EP4CE55F23C8N Altera, EP4CE55F23C8N Datasheet - Page 386

• Manufacturer Part Number: EP4CE55F23C8N
• Description: IC CYCLONE IV FPGA 55K 484FBGA
• Manufacturer: Altera
• Series: CYCLONE® IV Er

Specifications of EP4CE55F23C8N

• Number Of Logic Elements/cells: 55856
• Number Of Labs/clbs: 3491
• Total Ram Bits: 2340000
• Number Of I /o: 324
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Family Name: Cyclone IV
• Number Of Logic Blocks/elements: 55856
• # I/os (max): 324
• Logic Cells: 55856
• Ram Bits: 2396160
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

2–20
Cyclone IV Device Handbook, Volume 2
As shown in
dynamic reconfiguration controller to change the configuration of the transceiver
channel:
1. After power up and establishing that the transceiver is operating as desired, write
2. Assert the tx_digitalreset, rx_analogreset, and rx_digitalreset
3. As soon as write_all is asserted, the dynamic reconfiguration controller starts
4. Wait for the assertion of the channel_reconfig_done signal (marker 4) that
5. Deassert the tx_digitalreset signal (marker 5). This signal must be
6. Wait for at least five parallel clock cycles after assertion of the
7. Lastly, wait for the rx_freqlocked signal to go high. After rx_freqlocked
the desired new value in the appropriate registers (including
reconfig_mode_sel[2:0]) and subsequently assert the write_all signal
(marker 1) to initiate the dynamic reconfiguration.
f
signals.
to execute its operation. This is indicated by the assertion of the busy signal
(marker 2).
indicates the completion of dynamic reconfiguration in this mode.
deasserted after assertion of the channel_reconfig_done signal (marker 4)
and before the deassertion of the rx_analogreset signal (marker 6).
channel_reconfig_done signal (marker 4) to deassert the rx_analogreset
signal (marker 6).
goes high (marker 7), wait for t
(marker 8). At this point, the receiver is ready for data traffic.
For more information, refer to the
chapter.
Figure
2–12, perform the following reset procedure when using the
LTD_Auto
to deassert the rx_digitalreset signal
Chapter 2: Cyclone IV Reset Control and Power Down
Cyclone IV Dynamic Reconfiguration
Dynamic Reconfiguration Reset Sequences
© December 2010 Altera Corporation