EP4CE55F23C8N Altera, EP4CE55F23C8N Datasheet - Page 289

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EP4CE55F23C8N

Manufacturer Part Number
EP4CE55F23C8N
Description
IC CYCLONE IV FPGA 55K 484FBGA
Manufacturer
Altera
Series
CYCLONE® IV Er

Specifications of EP4CE55F23C8N

Number Of Logic Elements/cells
55856
Number Of Labs/clbs
3491
Total Ram Bits
2340000
Number Of I /o
324
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
484-FBGA
Family Name
Cyclone IV
Number Of Logic Blocks/elements
55856
# I/os (max)
324
Logic Cells
55856
Ram Bits
2396160
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
484
Package Type
FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant

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Chapter 1: Cyclone IV Transceivers Architecture
Transmitter Channel Datapath
Transmitter Output Buffer
© December 2010 Altera Corporation
f
1
Figure 1–11
Figure 1–11. Transmitter Output Buffer Block Diagram
Note to
(1) Receiver detect function is specific for PCIe protocol implementation only. For more information, refer to
The Cyclone IV GX transmitter output buffers support the 1.5-V PCML I/O standard
and are powered by VCCH_GXB power pins with 2.5-V supply. The 2.5-V supply on
VCCH_GXB pins are regulated internally to 1.5-V for the transmitter output buffers.
The transmitter output buffers support the following additional features:
Disable OCT to use external termination if the link requires a 85  termination, such
as when you are interfacing with certain PCIe Gen1 or Gen2 capable devices.
The Cyclone IV GX transmitter output buffers are current-mode drivers. The resulting
V
supported V
OD
Programmable differential output voltage (V
1200 mV to handle different trace lengths, various backplanes, and various
receiver requirements.
Programmable pre-emphasis—boosts high-frequency components in the
transmitted signal to maximize the data eye opening at the far-end. The
high-frequency components might be attenuated in the transmission media due to
data-dependent jitter and intersymbol interference (ISI) effects. The requirement
for pre-emphasis increases as the data rates through legacy backplanes increase.
Programmable differential on-chip termination (OCT)—provides calibrated OCT
at differential 100  or 150 with on-chip transmitter common mode voltage
(V
termination.
Express (PIPE) Mode” on page
voltage is therefore a function of the transmitter termination value. For lists of
CM
Figure
) at 0.65 V. V
1–11:
shows the transmitter output buffer block diagram.
OD
settings, refer to the
Programmable
Pre-emphasis
and V
CM
OD
is tri-stated when you disable the OCT to use external
1–48.
Cyclone IV Device Data
Detect (1)
Receiver
OD
50 or 75 
50 or 75 
)—customizes the V
+ V
Cyclone IV Device Handbook, Volume 2
CM
Sheet.
-
GXB_TXp
GXB_TXn
OD
up to
“PCI
1–9

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