EP4CE55F23C8N Altera, EP4CE55F23C8N Datasheet - Page 346

• Manufacturer Part Number: EP4CE55F23C8N
• Description: IC CYCLONE IV FPGA 55K 484FBGA
• Manufacturer: Altera
• Series: CYCLONE® IV Er

Specifications of EP4CE55F23C8N

• Number Of Logic Elements/cells: 55856
• Number Of Labs/clbs: 3491
• Total Ram Bits: 2340000
• Number Of I /o: 324
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Family Name: Cyclone IV
• Number Of Logic Blocks/elements: 55856
• # I/os (max): 324
• Logic Cells: 55856
• Ram Bits: 2396160
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

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Figure 1–65. Deskew FIFO–Lane Skew at the Receiver Input
Cyclone IV Device Handbook, Volume 2
Lane 0
Lane 2
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Lane 1
Lane 3
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Lane 0
Lane 1
Lane 2
Lane 3
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Figure 1–65
/A/ code group to align the channels.
Lane Synchronization
In XAUI mode, the word aligner is configured in automatic synchronization state
machine mode that is compliant to the PCS synchronization state diagram specified in
clause 48 of the IEEE P802.3ae specification.
machine parameters that implements the lane synchronization in XAUI mode.
Table 1–23. Synchronization State Machine Parameters
Number of valid synchronization (/K28.5/) code groups received to achieve
synchronization
Number of erroneous code groups received to lose synchronization
Number of continuous good code groups received to reduce the error count by
one
Note to
(1) The word aligner supports 7-bit and 10-bit pattern lengths in XAUI mode.
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Channel alignment is acquired if three additional aligned ||A|| columns are
observed at the output of the deskew FIFOs of the four channels after alignment of
the first ||A|| column.
Channel alignment is indicated by the assertion of rx_channelaligned signal.
After acquiring channel alignment, if four misaligned ||A|| columns are seen at
the output of the deskew FIFOs in all four channels with no aligned ||A||
columns in between, the rx_channelaligned signal is deasserted, indicating
loss of channel alignment.
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Table
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1–23:
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shows lane skew at the receiver input and how the deskew FIFO uses the
/A/ column
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Parameter
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Table 1–23
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Chapter 1: Cyclone IV Transceivers Architecture
(Note 1)
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lists the synchronization state
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© December 2010 Altera Corporation
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Transceiver Functional Modes
Lanes skew at
receiver input
Lanes are deskewed by lining
up the “Align”/A/ code groups
Value
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4