EP4CE55F23C8N Altera, EP4CE55F23C8N Datasheet - Page 252

• Manufacturer Part Number: EP4CE55F23C8N
• Description: IC CYCLONE IV FPGA 55K 484FBGA
• Manufacturer: Altera
• Series: CYCLONE® IV Er

Specifications of EP4CE55F23C8N

• Number Of Logic Elements/cells: 55856
• Number Of Labs/clbs: 3491
• Total Ram Bits: 2340000
• Number Of I /o: 324
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Family Name: Cyclone IV
• Number Of Logic Blocks/elements: 55856
• # I/os (max): 324
• Logic Cells: 55856
• Ram Bits: 2396160
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

9–6
Table 9–6. CRC Calculation Time
Cyclone IV Device Handbook, Volume 1
Cyclone IV E
Cyclone IV GX
Notes to
(1) The minimum time corresponds to the maximum error detection clock frequency and may vary with different processes, voltages, and
(2) The maximum time corresponds to the minimum error detection clock frequency and may vary with different PVT.
(3) Only applicable for device with 1.2-V core voltage
(4) Only applicable for the F484 device package.
temperatures (PVT).
Table
9–6:
You can set a lower clock frequency by specifying a division factor in the Quartus II
software (for more information, refer to
of two (2), where n is between 0 and 8. The divisor ranges from one through 256. Refer
to
Equation 9–1.
CRC calculation time depends on the device and the error detection clock frequency.
Table 9–6
maximum clock frequencies for Cyclone IV devices.
Device
Equation
EP4CE6
EP4CE10
EP4CE15
EP4CE22
EP4CE30
EP4CE40
EP4CE55
EP4CE75
EP4CE115
EP4CGX15
EP4CGX22
EP4CGX30
EP4CGX50
EP4CGX75
EP4CGX110
EP4CGX150
lists the estimated time for each CRC calculation with minimum and
(3)
9–1.
(3)
(3)
(3)
(3)
(3)
(3)
(3)
(3)
Error detection frequency
Minimum Time (ms)
34
“Software
15
15
23
31
45
12
12
34
34
62
62
5
5
7
9
6
(4)
(1)
=
Chapter 9: SEU Mitigation in Cyclone IV Devices
Support”). The divisor is a power
------------------ -
80 MHz
2
n
© February 2010 Altera Corporation
Maximum Time (s)
17.34
11.77
15.81
22.67
17.34
17.34
31.27
31.27
2.29
2.29
3.17
4.51
7.48
7.48
2.93
5.95
5.95
Error Detection Timing
(4)
(2)