EP4CE55F23C8N Altera, EP4CE55F23C8N Datasheet - Page 369

• Manufacturer Part Number: EP4CE55F23C8N
• Description: IC CYCLONE IV FPGA 55K 484FBGA
• Manufacturer: Altera
• Series: CYCLONE® IV Er

Specifications of EP4CE55F23C8N

• Number Of Logic Elements/cells: 55856
• Number Of Labs/clbs: 3491
• Total Ram Bits: 2340000
• Number Of I /o: 324
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Family Name: Cyclone IV
• Number Of Logic Blocks/elements: 55856
• # I/os (max): 324
• Logic Cells: 55856
• Ram Bits: 2396160
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 2: Cyclone IV Reset Control and Power Down
User Reset and Power-Down Signals
Table 2–2. Transceiver Block Power-Down Signals (Part 2 of 2)
Blocks Affected by the Reset and Power-Down Signals
Table 2–3. Blocks Affected by Reset and Power-Down Signals (Part 1 of 2)
© December 2010 Altera Corporation
rx_freqlocked
busy
multipurpose PLLs and
general purpose PLLs
Transmitter Phase
Compensation FIFO
Byte Serializer
8B/10B Encoder
Serializer
Transmitter Buffer
Transmitter XAUI State
Machine
Receiver Buffer
Receiver CDR
Receiver Deserializer
Receiver Word Aligner
Receiver Deskew FIFO
Receiver Clock Rate
Compensation FIFO
Receiver 8B/10B
Decoder
Receiver Byte
Deserializer
Transceiver Block
Signal
1
1
For more information about offset cancellation, refer to the
Reconfiguration
If none of the channels is instantiated in a transceiver block, the Quartus
automatically powers down the entire transceiver block.
Table 2–3
rx_digitalreset
A status signal. Indicates the status of the receiver CDR lock mode.
■
■
A status signal. An output from the ALTGX_RECONFIG block indicates the status of the
dynamic reconfiguration controller. This signal remains low for the first reconfig_clk
clock cycle after power up. It then gets asserted from the second reconfig_clk clock
cycle. Assertion on this signal indicates that the offset cancellation process is being
executed on the receiver buffer as well as the receiver CDR. When this signal is
deasserted, it indicates that offset cancellation is complete.
This busy signal is also used to indicate the dynamic reconfiguration duration such as in
analog reconfiguration mode and channel reconfiguration mode.
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lists the blocks that are affected by specific reset and power-down signals.
A high level—the receiver is in lock-to-data mode.
A low level—the receiver CDR is in lock-to-reference mode.
chapter.
rx_analogreset
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tx_digitalreset
Description
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pll_areset
Cyclone IV Device Handbook, Volume 2
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Cyclone IV Dynamic
gxb_powerdown
®
II software
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2–3