EP4CE55F23C8N Altera, EP4CE55F23C8N Datasheet - Page 318

• Manufacturer Part Number: EP4CE55F23C8N
• Description: IC CYCLONE IV FPGA 55K 484FBGA
• Manufacturer: Altera
• Series: CYCLONE® IV Er

Specifications of EP4CE55F23C8N

• Number Of Logic Elements/cells: 55856
• Number Of Labs/clbs: 3491
• Total Ram Bits: 2340000
• Number Of I /o: 324
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Family Name: Cyclone IV
• Number Of Logic Blocks/elements: 55856
• # I/os (max): 324
• Logic Cells: 55856
• Ram Bits: 2396160
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

1–38
Cyclone IV Device Handbook, Volume 2
In configuration with rate match FIFO, the transmitter datapath clocking is identical
to Transmitter Only operation as shown in
channel, the CDR unit recovers the clock from serial received data and generates the
high- and low-speed recovered clock for each bonded channel. The high-speed
recovered clock feeds the channel's deserializer, and low-speed recovered clock is
forwarded to receiver PCS. The individual low-speed recovered clock feeds to the
following blocks in the receiver PCS:
■
■
The common bonded low-speed clock that is used in all bonded transmitter PCS
datapaths feeds the following blocks in each bonded receiver PCS:
■
■
■
■
■
When the byte deserializer is enabled, the common bonded low-speed clock
frequency is halved before feeding to the write clock of RX phase compensation FIFO.
The common bonded low-speed clock is available in FPGA fabric as coreclkout
port, which can be used in FPGA fabric to send transmitter data and control signals,
and capture receiver data and status signals from the bonded channels.
word aligner
write clock of rate match FIFO
read clock of rate match FIFO
8B/10B decoder
write clock of byte deserializer
byte ordering
write clock of RX phase compensation FIFO
Figure
Chapter 1: Cyclone IV Transceivers Architecture
1–38. In each bonded receiver
© December 2010 Altera Corporation
Transceiver Clocking Architecture