EP4CE55F23C8N Altera, EP4CE55F23C8N Datasheet - Page 249

• Manufacturer Part Number: EP4CE55F23C8N
• Description: IC CYCLONE IV FPGA 55K 484FBGA
• Manufacturer: Altera
• Series: CYCLONE® IV Er

Specifications of EP4CE55F23C8N

• Number Of Logic Elements/cells: 55856
• Number Of Labs/clbs: 3491
• Total Ram Bits: 2340000
• Number Of I /o: 324
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Family Name: Cyclone IV
• Number Of Logic Blocks/elements: 55856
• # I/os (max): 324
• Logic Cells: 55856
• Ram Bits: 2396160
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 9: SEU Mitigation in Cyclone IV Devices
Automated SEU Detection
Table 9–1. CHANGE_EDREG JTAG Instruction
Automated SEU Detection
CRC_ERROR Pin
Table 9–2. Cyclone IV Device CRC_ERROR Pin Description
© February 2010 Altera Corporation
CHANGE_EDREG
JTAG Instruction
Dedicated Output or Open
Drain Output (Optional)
CRC_ERROR Pin Type
1
Instruction Code
In user mode, Cyclone IV devices support the CHANGE_EDREG JTAG instruction, that
allows you to write to the 32-bit storage register. You can use Jam
to automate the testing and verification process. You can only execute this instruction
when the device is in user mode, and it is a powerful design feature that enables you
to dynamically verify the CRC functionality in-system without having to reconfigure
the device. You can then use the CRC circuit to check for real errors induced by an
SEU.
Table 9–1
00 0001 0101
After the test completes, Altera recommends that you power cycle the device.
Cyclone IV devices offer on-chip circuitry for automated checking of SEU detection.
Applications that require the device to operate error-free at high elevations or in close
proximity to earth’s north or south pole require periodic checks to ensure continued
data integrity. The error detection cyclic redundancy code feature controlled by the
Device and Pin Options dialog box in the Quartus II software uses a 32-bit CRC
circuit to ensure data reliability and is one of the best options for mitigating SEU.
You can implement the error detection CRC feature with existing circuitry in
Cyclone IV devices, eliminating the need for external logic. The CRC is computed by
the device during configuration and checked against an automatically computed CRC
during normal operation. The CRC_ERROR pin reports a soft error when configuration
CRAM data is corrupted. You must decide whether to reconfigure the FPGA by
strobing the nCONFIG pin low or ignore the error.
A specific CRC_ERROR error detection pin is required to monitor the results of the
error detection circuitry during user mode.
By default, the Quartus II software sets the CRC_ERROR pin as a dedicated output. If the
CRC_ERROR pin is used as a dedicated output, you must ensure that the V
in which the pin resides meets the input voltage specification of the system receiving the
signal. Optionally, you can set this pin to be an open-drain output by enabling the option in
the Quartus II software from the Error Detection CRC tab of the Device and Pin Options
dialog box. Using the pin as an open-drain provides an advantage on the voltage leveling.
To use this pin as open-drain, you can tie this pin to V
resistor. Alternatively, depending on the voltage input specification of the system receiving
the signal, you can tie the pull-up resistor to a different pull-up voltage.
describes the CHANGE_EDREG JTAG instructions.
This instruction connects the 32-bit CRC storage register between TDI and TDO.
Any precomputed CRC is loaded into the CRC storage register to test the operation
of the error detection CRC circuitry at the CRC_ERROR pin.
Description
Table 9–2
Description
CCIO
describes the CRC_ERROR pin.
of Bank 1 through a 10-k pull-up
Cyclone IV Device Handbook, Volume 1
™
STAPL files (.jam)
CCIO
of the bank
9–3