EP4CE55F23C8N Altera, EP4CE55F23C8N Datasheet - Page 310

• Manufacturer Part Number: EP4CE55F23C8N
• Description: IC CYCLONE IV FPGA 55K 484FBGA
• Manufacturer: Altera
• Series: CYCLONE® IV Er

Specifications of EP4CE55F23C8N

• Number Of Logic Elements/cells: 55856
• Number Of Labs/clbs: 3491
• Total Ram Bits: 2340000
• Number Of I /o: 324
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Family Name: Cyclone IV
• Number Of Logic Blocks/elements: 55856
• # I/os (max): 324
• Logic Cells: 55856
• Ram Bits: 2396160
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

1–30
Cyclone IV Device Handbook, Volume 2
Figure 1–32. Clock Distribution in Non-Bonded Channel Configuration for Transceivers in F484 and
Larger Packages
Notes to
(1) High-speed clock.
(2) Low-speed clock.
(3) These PLLs have restricted clock driving capability and may not reach all connected channels. For details, refer to
The transceiver datapath clocking varies in non-bonded channel configuration
depending on the PCS configuration.
Figure 1–33
each channel selects the high- and low-speed clock from one of the supported PLLs.
The high-speed clock feeds to the serializer for parallel to serial operation. The
low-speed clock feeds to the following blocks in the transmitter PCS:
■
■
■
When the byte serializer is enabled, the low-speed clock frequency is halved before
feeding into the read clock of TX phase compensation FIFO. The low-speed clock is
available in the FPGA fabric as tx_clkout port, which can be used in the FPGA
fabric to send transmitter data and control signals.
8B/10B encoder
read clock of the byte serializer
read clock of the TX phase compensation FIFO
Table
Figure 1–32
1–9.
shows the datapath clocking in transmitter only operation. In this mode,
:
Transceiver
Transceiver
GXBL1
GXBL0
Block
Block
Ch3
Ch2
Ch1
Ch0
Ch3
Ch2
Ch1
Ch0
MPLL_8
MPLL_7
MPLL_6
MPLL_5
(3)
(3)
TX PMA
TX PMA
TX PMA
TX PMA
TX PMA
TX PMA
TX PMA
TX PMA
(2)
(2)
(1)
Chapter 1: Cyclone IV Transceivers Architecture
(1)
Not applicable in
F484 package
GPLL_2
GPLL_1
(3)
(3)
© December 2010 Altera Corporation
Transceiver Clocking Architecture