EP4CE55F23C8N Altera, EP4CE55F23C8N Datasheet - Page 282

• Manufacturer Part Number: EP4CE55F23C8N
• Description: IC CYCLONE IV FPGA 55K 484FBGA
• Manufacturer: Altera
• Series: CYCLONE® IV Er

Specifications of EP4CE55F23C8N

• Number Of Logic Elements/cells: 55856
• Number Of Labs/clbs: 3491
• Total Ram Bits: 2340000
• Number Of I /o: 324
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Family Name: Cyclone IV
• Number Of Logic Blocks/elements: 55856
• # I/os (max): 324
• Logic Cells: 55856
• Ram Bits: 2396160
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

1–2
Transceiver Architecture
Cyclone IV Device Handbook, Volume 2
Cyclone IV GX devices offer either one or two transceiver blocks per device,
depending on the package. Each block consists of four full-duplex (transmitter and
receiver) channels, located on the left side of the device (in a die-top view).
and
locations in Cyclone IV GX devices.
Figure 1–1. F324 and Smaller Packages with Transceiver Channels for Cyclone IV GX Devices
Note to
(1) Channel 2 and Channel 3 are not available in the F169 and smaller packages.
Figure 1–2. F484 and Larger Packages with Transceiver Channels for Cyclone IV GX Devices
Figure 1–2
Figure
1–1:
show the die-top view of the transceiver block and related resource
Block GXBL1
Block GXBL0
Block GXBL0
Transceiver
Transceiver
Transceiver
MPLL_8 GPLL_2
MPLL_7
MPLL_6
MPLL_5
Calibration Block
Channel 3
Channel 2
Channel 1
Channel 0
Channel 3
Channel 2
Channel 1
Channel 0
MPLL_2
MPLL_1
Calibration Block
Channel 3 (1)
Channel 2 (1)
Channel 1
Channel 0
GPLL_1
Not applicable in
hard IP
F484 package
PCIe
hard IP
PCIe
Chapter 1: Cyclone IV Transceivers Architecture
F324 and smaller
packages
© December 2010 Altera Corporation
F484 and larger
packages
Transceiver Architecture
Figure 1–1