EP4CE55F23C8N Altera, EP4CE55F23C8N Datasheet - Page 283

• Manufacturer Part Number: EP4CE55F23C8N
• Description: IC CYCLONE IV FPGA 55K 484FBGA
• Manufacturer: Altera
• Series: CYCLONE® IV Er

Specifications of EP4CE55F23C8N

• Number Of Logic Elements/cells: 55856
• Number Of Labs/clbs: 3491
• Total Ram Bits: 2340000
• Number Of I /o: 324
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Family Name: Cyclone IV
• Number Of Logic Blocks/elements: 55856
• # I/os (max): 324
• Logic Cells: 55856
• Ram Bits: 2396160
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 1: Cyclone IV Transceivers Architecture
Architectural Overview
Architectural Overview
Figure 1–3. Transceiver Channel Datapath for Cyclone IV GX Devices
© December 2010 Altera Corporation
rx_dataout
Fabric
FPGA
tx_datain
For more information about the transceiver architecture, refer to the following
sections:
■
■
■
■
■
■
■
■
Figure 1–3
Each transceiver channel consists of a transmitter and a receiver datapath. Each
datapath is further structured into the following:
■
■
Outbound parallel data from the FPGA fabric flows through the transmitter PCS and
PMA, is transmitted as serial data. Received inbound serial data flows through the
receiver PMA and PCS into the FPGA fabric. The transceiver supports the following
interface widths:
■
■
“Architectural Overview” on page 1–3
“Transmitter Channel Datapath” on page 1–4
“Receiver Channel Datapath” on page 1–10
“Transceiver Clocking Architecture” on page 1–24
“Transceiver Channel Datapath Clocking” on page 1–26
“FPGA Fabric-Transceiver Interface Clocking” on page 1–39
“Calibration Block” on page 1–41
“PCI-Express Hard IP Block” on page 1–42
Physical media attachment (PMA)—includes analog circuitry for I/O buffers,
clock data recovery (CDR), serializer/deserializer (SERDES), and programmable
pre-emphasis and equalization to optimize serial data channel performance.
Physical coding sublayer (PCS)—includes hard logic implementation of digital
functionality within the transceiver that is compliant with supported protocols.
FPGA fabric-transceiver PCS—8, 10, 16, or 20 bits
PMA-PCS—8 or 10 bits
Phase
Comp
FIFO
Rx
shows the Cyclone IV GX transceiver channel datapath.
wr_clk
Tx Phase
Comp
FIFO
rd_clk
Order-
Byte
ing
serializer
Byte
De-
wr_clk
Byte Serializer
Transmitter Channel PCS
Decoder
8B/10B
rd_clk
Receiver Channel PCS
Match
FIFO
Rate
8B/10B Encoder
Deskew
FIFO
Cyclone IV Device Handbook, Volume 2
Aligner
Word
Deserial-
Transmitter Channel PMA
Receiver Channel PMA
izer
Serializer
CDR
1–3