EP4CE55F23C8N Altera, EP4CE55F23C8N Datasheet - Page 360

• Manufacturer Part Number: EP4CE55F23C8N
• Description: IC CYCLONE IV FPGA 55K 484FBGA
• Manufacturer: Altera
• Series: CYCLONE® IV Er

Specifications of EP4CE55F23C8N

• Number Of Logic Elements/cells: 55856
• Number Of Labs/clbs: 3491
• Total Ram Bits: 2340000
• Number Of I /o: 324
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Family Name: Cyclone IV
• Number Of Logic Blocks/elements: 55856
• # I/os (max): 324
• Logic Cells: 55856
• Ram Bits: 2396160
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

1–80
Table 1–27. Receiver Ports in ALTGX Megafunction for Cyclone IV GX (Part 1 of 3)
Cyclone IV Device Handbook, Volume 2
RX PCS
Block
rx_syncstatus
rx_patternde
tect
rx_bitslip
rx_rlv
rx_invpolarity
rx_enapattern
align
rx_rmfifodata
inserted
rx_rmfifodata
deleted
Port Name
Output
Output
Output
Output
Output
Output
Input/
Input
Input
Input
Synchronous to tx_clkout (non-
bonded modes with rate match FIFO),
rx_clkout (non-bonded modes
without rate match FIFO),
coreclkout (bonded modes), or
rx_coreclk (when using the
optional rx_coreclk input)
Synchronous to tx_clkout (non-
bonded modes with rate match FIFO),
rx_clkout (non-bonded modes
without rate match FIFO),
coreclkout (bonded modes), or
rx_coreclk (when using the
optional rx_coreclk input)
Asynchronous signal. Minimum pulse
width is two
parallel clock cycles.
Asynchronous signal. Driven for a
minimum of two recovered clock
cycles in configurations without byte
serializer and a minimum of three
recovered clock cycles in
configurations with byte serializer.
Asynchronous signal. Minimum pulse
width is two parallel clock cycles.
Asynchronous signal.
Synchronous to tx_clkout (non-
bonded modes) or coreclkout
(bonded modes)
Synchronous to tx_clkout (non-
bonded modes) or coreclkout
(bonded modes)
Clock Domain
Chapter 1: Cyclone IV Transceivers Architecture
Word alignment synchronization status indicator. This
signal passes through the RX Phase Compensation FIFO.
■
Indicates when the word alignment logic detects the
alignment pattern in the current word boundary. This signal
passes through the RX Phase Compensation FIFO.
Bit-slip control for the word aligner configured in bit-slip
mode.
■
Run-length violation indicator.
■
Generic receiver polarity inversion control.
■
Controls the word aligner operation configured in manual
alignment mode.
Rate match FIFO insertion status indicator.
■
Rate match FIFO deletion status indicator.
■
Not available in bit-slip mode
At every rising edge, word aligner slips one bit into the
received data stream, effectively shifting the word
boundary by one bit.
A high pulse indicates that the number of consecutive 1s
or 0s in the received data stream exceeds the
programmed run length violation threshold.
A high level to invert the polarity of every bit of the 8- or
10-bit data to the word aligner.
A high level indicates the rate match pattern byte is
inserted to compensate for the PPM difference in the
reference clock frequencies between the upstream
transmitter and the local receiver.
A high level indicates the rate match pattern byte is
deleted to compensate for the PPM difference in the
reference clock frequencies between the upstream
transmitter and the local receiver.
© December 2010 Altera Corporation
Transceiver Top-Level Port Lists
Description