EP4CE55F23C8N Altera, EP4CE55F23C8N Datasheet - Page 287

• Manufacturer Part Number: EP4CE55F23C8N
• Description: IC CYCLONE IV FPGA 55K 484FBGA
• Manufacturer: Altera
• Series: CYCLONE® IV Er

Specifications of EP4CE55F23C8N

• Number Of Logic Elements/cells: 55856
• Number Of Labs/clbs: 3491
• Total Ram Bits: 2340000
• Number Of I /o: 324
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Family Name: Cyclone IV
• Number Of Logic Blocks/elements: 55856
• # I/os (max): 324
• Logic Cells: 55856
• Ram Bits: 2396160
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 1: Cyclone IV Transceivers Architecture
Transmitter Channel Datapath
© December 2010 Altera Corporation
K28.5 at time n + 2 is encoded as a positive disparity code group. In the same example,
the current running disparity at time n + 5 indicates that the K28.5 in time n + 6 should
be encoded with a positive disparity. Because tx_forcedisp is high at time n + 6,
and tx_dispval is high, the K28.5 at time n + 6 is encoded as a negative disparity
code group.
Miscellaneous Transmitter PCS Features
The transmitter PCS supports the following additional features:
■
Figure 1–9. Transmitter Polarity Inversion
■
Polarity inversion—corrects accidentally swapped positive and negative signals
from the serial differential link during board layout by inverting the polarity of
each bit. An optional tx_invpolarity port is available to dynamically invert the
polarity of every bit of the 8-bit or 10-bit input data to the serializer in the
transmitter datapath.
1
Bit reversal—reverses the transmit bit order from LSB-to-MSB (default) to
MSB-to-LSB at the input to the serializer. For example, input data to serializer
D[7..0] is rewired to D[0..7] for 8-bit data width, and D[9..0] is rewired to
D[0..9] for 10-bit data width.
feature.
tx_invpolarity is a dynamic signal and might cause initial disparity
errors at the receiver of an 8B/10B encoded link. The downstream system
must be able to tolerate these disparity errors.
Output from transmitter PCS
Figure 1–9
0
1
1
1
0
0
0
1
0
0
MSB
LSB
tx_invpolarity = HIGH
Figure 1–10
shows the transmitter polarity inversion feature.
Converted data output to the
shows the transmitter bit reversal
transmitter serializer
1
0
0
0
1
1
1
0
1
1
Cyclone IV Device Handbook, Volume 2
MSB
LSB
1–7