EP4CE55F23C8N Altera, EP4CE55F23C8N Datasheet - Page 415

• Manufacturer Part Number: EP4CE55F23C8N
• Description: IC CYCLONE IV FPGA 55K 484FBGA
• Manufacturer: Altera
• Series: CYCLONE® IV Er

Specifications of EP4CE55F23C8N

• Number Of Logic Elements/cells: 55856
• Number Of Labs/clbs: 3491
• Total Ram Bits: 2340000
• Number Of I /o: 324
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Family Name: Cyclone IV
• Number Of Logic Blocks/elements: 55856
• # I/os (max): 324
• Logic Cells: 55856
• Ram Bits: 2396160
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 3: Cyclone IV Dynamic Reconfiguration
Dynamic Reconfiguration Modes
Figure 3–10. ALTGX and ALTGX_RECONFIG Connection for Channel Reconfiguration Mode
Note to
(1) This block can be reconfigured in channel reconfiguration mode.
© December 2010 Altera Corporation
Figure
reconfig_clk
reconfig_reset
write_all
reconfig_data[15..0]
reset_reconfig_address
logical_channel_address[n..0]
3–10:
Control and Status Signals for Channel Reconfiguration
The various control and status signals involved in the Channel Reconfiguration mode
are as follows. Refer to
for the descriptions of the control and status signals.
■
■
■
■
■
The following are output status signals:
■
■
■
■
The ALTGX_RECONFIG connection to the ALTGX instances when set in channel
reconfiguration mode are as follows. For the port information, refer to
Reconfiguration Controller Port List” on page
Figure 3–10
Clocking/Interface Options
The following describes the Clocking/Interface options available in Cyclone IV GX
devices. The core clocking setup describes the transceiver core clocks that are the
write and read clocks of the Transmit Phase Compensation FIFO and the Receive
Phase Compensation FIFO, respectively. Core clocking is classified as transmitter core
clocking and receiver core clocking.
The following are the input control signals:
logical_channel_address[n..0]
reset_reconfig_address
reconfig_reset
reconfig_mode_sel[2..0]
write_all
reconfig_address_en
reconfig_address_out[5..0]
channel_reconfig_done
busy
Output status signals from the ALTGX_RECONFIG controller
Input control signals to the ALTGX_RECONFIG controller
ALTGX_RECONFIG
shows the connection for channel reconfiguration mode.
Reconfig
Channel
Control
Logic
“Dynamic Reconfiguration Controller Port List” on page 3–3
reconfig_togxb[3..0]
busy
channel_reconfig_done
reconfig_address_out[5..0]
reconfig_address_en
reconfig_fromgxb[n..0]
3–3.
RX PCS
TX PCS
Cyclone IV Device Handbook, Volume 2
(1)
(1)
ALTGX
TX PMA
+ CDR (1)
RX PMA
“Dynamic
3–25