EP4CE55F23C8N Altera, EP4CE55F23C8N Datasheet - Page 417

• Manufacturer Part Number: EP4CE55F23C8N
• Description: IC CYCLONE IV FPGA 55K 484FBGA
• Manufacturer: Altera
• Series: CYCLONE® IV Er

Specifications of EP4CE55F23C8N

• Number Of Logic Elements/cells: 55856
• Number Of Labs/clbs: 3491
• Total Ram Bits: 2340000
• Number Of I /o: 324
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Family Name: Cyclone IV
• Number Of Logic Blocks/elements: 55856
• # I/os (max): 324
• Logic Cells: 55856
• Ram Bits: 2396160
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 3: Cyclone IV Dynamic Reconfiguration
Dynamic Reconfiguration Modes
Figure 3–11. Option 1 for Transmitter Core Clocking (Channel Reconfiguration Mode)
© December 2010 Altera Corporation
FPGA Fabric
tx_clkout[0]
Low-speed parallel clock (tx_clkout0)
High-speed serial clock generated by the MPLL
Figure 3–11
channels of a transceiver block.
Option 2: Use the Respective Channel Transmitter Core Clocks
■
■
Enable this option if you want the individual transmitter channel tx_clkout
signals to provide the write clock to their respective Transmit Phase Compensation
FIFOs.
This option is typically enabled when each transceiver channel is reconfigured to a
different functional mode using channel reconfiguration.
shows the sharing of channel 0’s tx_clkout between all four regular
Transceiver Block
RX0
RX1
RX2
RX3
TX0
TX1
TX2
TX3
Cyclone IV Device Handbook, Volume 2
MPLL
3–27