EP4CE55F23C8N Altera, EP4CE55F23C8N Datasheet - Page 57

• Manufacturer Part Number: EP4CE55F23C8N
• Description: IC CYCLONE IV FPGA 55K 484FBGA
• Manufacturer: Altera
• Series: CYCLONE® IV Er

Specifications of EP4CE55F23C8N

• Number Of Logic Elements/cells: 55856
• Number Of Labs/clbs: 3491
• Total Ram Bits: 2340000
• Number Of I /o: 324
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Family Name: Cyclone IV
• Number Of Logic Blocks/elements: 55856
• # I/os (max): 324
• Logic Cells: 55856
• Ram Bits: 2396160
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 4: Embedded Multipliers in Cyclone IV Devices
Architecture
Architecture
Input Registers
Multiplier Stage
© February 2010 Altera Corporation
Each embedded multiplier consists of the following elements:
■
■
■
Figure 4–2
Figure 4–2. Multiplier Block Architecture
You can send each multiplier input signal into an input register or directly into the
multiplier in 9- or 18-bit sections, depending on the operational mode of the
multiplier. You can send each multiplier input signal through a register independently
of other input signals. For example, you can send the multiplier Data A signal
through a register and send the Data B signal directly to the multiplier.
The following control signals are available for each input register in the embedded
multiplier:
■
■
■
All input and output registers in a single embedded multiplier are fed by the same
clock, clock enable, and asynchronous clear signals.
The multiplier stage of an embedded multiplier block supports 9 × 9 or 18 × 18
multipliers, as well as other multipliers between these configurations. Depending on
the data width or operational mode of the multiplier, a single embedded multiplier
can perform one or two multiplications in parallel. For multiplier information, refer to
“Operational Modes” on page
Multiplier stage
Input and output registers
Input and output interfaces
clock
clock enable
asynchronous clear
shows the multiplier block architecture.
Data A
Data B
D
ENA
D
ENA
CLRN
CLRN
signa
signb
clock
Q
Q
ena
aclr
4–4.
Register
Input
Embedded Multiplier Block
D
ENA
CLRN
Register
Output
Q
Cyclone IV Device Handbook, Volume 1
Data Out
4–3