LPC47B272-MS SMSC, LPC47B272-MS Datasheet - Page 103

• Manufacturer Part Number: LPC47B272-MS
• Description: IC CTRLR SUPER I/O LPC 100-QFP
• Manufacturer: SMSC

Specifications of LPC47B272-MS

• Controller Type: I/O Controller
• Interface: LPC
• Voltage - Supply: 3.3V
• Current - Supply: 15mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 638-1019

Bit 0 of Port 92, which generates the nALT_RST signal, is used to reset the CPU under program
control. This signal is AND’ed together externally with the reset signal (nKBDRST) from the keyboard
controller to provide a software means of resetting the CPU. This provides a faster means of reset than
is provided by the keyboard controller. Writing a 1 to bit 0 in the Port 92 Register causes this signal to
pulse low for a minimum of 6µs, after a delay of a minimum of 14µs. Before another nALT_RST pulse
can be generated, bit 0 must be set to 0 either by a system reset of a write to Port 92. Upon reset, this
signal is driven inactive high (bit 0 in the Port 92 Register is set to 0).
If Port 92 is enabled, i.e., bit 2 of KRST_GA20 is set to 1, then a pulse is generated by writing a 1 to bit
0 of the Port 92 Register and this pulse is AND’ed with the pulse generated from the 8042. This pulse is
output on pin KRESET and its polarity is controlled by the GPI/O polarity configuration.
SMSC LPC47B27x
Bit
0
Function
driven low. Writing a 1 to this bit causes the ALT_A20 signal to be driven high.
Alternate System Reset. This read/write bit provides an alternate system reset
function. This function provides an alternate means to reset the system CPU to
effect a mode switch from Protected Virtual Address Mode to the Real Address
Mode. This provides a faster means of reset than is provided by the Keyboard
controller. This bit is set to a 0 by a system reset. Writing a 1 to this bit will cause
the nALT_RST signal to pulse active (low) for a minimum of 1 µs after a delay of
500 ns. Before another nALT_RST pulse can be generated, this bit must be written
back to a 0.
8042
P21
0
0
1
1
DATASHEET
Port 92 Register
nGATEA20
ALT_A20
0
1
0
1
- 103 -
System
nA20M
0
1
1
1
Rev. 04-17-07