LPC47B272-MS SMSC, LPC47B272-MS Datasheet - Page 28
![IC CTRLR SUPER I/O LPC 100-QFP](/photos/6/82/68212/qfp100-g1_pkg_sml.jpg)
LPC47B272-MS
Manufacturer Part Number
LPC47B272-MS
Description
IC CTRLR SUPER I/O LPC 100-QFP
Manufacturer
SMSC
Datasheet
1.LPC47B272-MS.pdf
(195 pages)
Specifications of LPC47B272-MS
Controller Type
I/O Controller
Interface
LPC
Voltage - Supply
3.3V
Current - Supply
15mA
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
100-QFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
638-1019
Available stocks
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Part Number
Manufacturer
Quantity
Price
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Part Number:
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Manufacturer:
ADI
Quantity:
957
Company:
Part Number:
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Manufacturer:
Microchip Technology
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Part Number:
LPC47B272-MS
Manufacturer:
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20 000
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Drive Rate Table (Recommended)
Note 1: The DRATE and DENSEL values are mapped onto the DRVDEN pins.
MAIN STATUS REGISTER
Address 3F4 READ ONLY
The Main Status Register is a read-only register and indicates the status of the disk controller. The Main Status Register
can be read at any time. The MSR indicates when the disk controller is ready to receive data via the Data Register. It
should be read before each byte transferring to or from the data register except in DMA mode. No delay is required
when reading the MSR after a data transfer.
BIT 0 - 1 DRV x BUSY
These bits are set to 1s when a drive is in the seek portion of a command, including implied and overlapped seeks and
recalibrates.
BIT 4 COMMAND BUSY
This bit is set to a 1 when a command is in progress. This bit will go active after the command byte has been accepted
and goes inactive at the end of the results phase. If there is no result phase (Seek, Recalibrate commands), this bit is
returned to a 0 after the last command byte.
BIT 5 NON-DMA
Reserved, read ‘0’. This part does not support non-DMA mode.
BIT 6 DIO
Indicates the direction of a data transfer once a RQM is set. A 1 indicates a read and a 0 indicates a write is required.
BIT 7 RQM
Indicates that the host can transfer data if set to a 1. No access is permitted if set to a 0.
SMSC LPC47B27x
RQM
7
DRT1
DRIVE RATE
DT1
1
1
1
0
1
0
1
DIO
6
DRT0
DT0
0
0
1
1
0
0
0
NON
DMA
5
Table 10 - Default Precompensation Delays
SEL1
00 = 360K, 1.2M, 720K, 1.44M and 2.88M Vertical Format
01 = 3-Mode Drive
10 = 2 Meg Tape
DATA RATE
DRVDEN1 (1)
0
0
1
DRATE0
DRATE0
DRATE0
DRATE1
DATA RATE
500 Kbps
300 Kbps
250 Kbps
2 Mbps
1 Mbps
BUSY
CMD
Table 9 - DRVDEN Mapping
SEL0
4
0
1
0
DATASHEET
Reserved Reserved
2Meg
MFM
500
250
DATA RATE
- 28 -
DRVDEN0 (1)
3
PRECOMPENSATION
nDENSEL
DENSEL
DRATE1
DRATE0
DELAYS
41.67 ns
250
125
FM
20.8 ns
---
125 ns
125 ns
125 ns
2
4/2/1 MB 3.5"
2/1 MB 5.25" FDDS
2/1.6/1 MB 3.5" (3-MODE)
PS/2
DENSEL
BUSY
DRV1
1
1
0
0
DRIVE TYPE
DRV0
BUSY
0
Rev. 04-17-07
DRATE(1)
1
0
0
1
0
0
1
0
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