LPC47B272-MS SMSC, LPC47B272-MS Datasheet - Page 149

• Manufacturer Part Number: LPC47B272-MS
• Description: IC CTRLR SUPER I/O LPC 100-QFP
• Manufacturer: SMSC

Specifications of LPC47B272-MS

• Controller Type: I/O Controller
• Interface: LPC
• Voltage - Supply: 3.3V
• Current - Supply: 15mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 638-1019

User Note:
User Note 1:
User Note 2:
User Note 3:
Note 1: If the EETI function is selected for this GPIO then both a high-to-low and a low-to-high edge
Note 2: The IRTX2 function can be used on this pin if the IR Location Mux bit in the Serial Port 2 IR
Note 3: The IR signal on RXD2 may affect both the GP52 PME status bit (bit 2 of PME_STS5) and the
Note 4: These pins default to an output and LOW on VCC POR and Hard Reset.
Note 5:
Note 6: The nIO_SMI pin is inactive when the internal group SMI signal is inactive and when the SMI
Note 7: Bits 2 and 3 of the PME_STS4 and SMI_STS4 registers, and bit 3 of the PME_STS5 register
Note 8. This GPIO defaults to a push-pull output following a VTR POR.
SMSC LPC47B27x
LED1
Default = 0x00
LED2
Default = 0x00
Keyboard Scan
Code
Default = 0x00
N/A
on VTR POR
on VTR POR
on VTR POR
NAME
will set the PME, SMI and MSC status bits
Option register is set
CIR PME status bit (bit 0 of PME_STS1). These two events are enabled independently of
each other via their associated status bits
of the FDD Mode Register (Configuration Register 0xF0 in Logical Device 0) will override bit 7
in the GPIO Control Register.
FDC function is selected.
enable bit (EN_SMI, bit 7 of the SMI_EN2 register) is ‘0’. When the output buffer type is OD,
nIO_SMI pin is floating when inactive; when the output buffer type is push-pull, the nIO_SMI
pin is high when inactive.
may be set on a VCC POR. If GP32, GP33 and GP53 are configured as input, then their
corresponding PME and SMI status bits will be set on a VCC POR. These GPIOs cannot be
used for PME wakeup when the part is under VTR power (VCC=0).
If the FDC function is selected on this pin (nMTR1, nDS1, DRVDEN0, DRVDEN1) then bit 6
When selecting an alternate function for a GPIO pin, all bits in the GPIO register must
be properly programmed, including in/out, polarity and output type. The polarity bit
does not affect the DDRC function or the either edge triggered interrupt functions.
If this pin is used for Ring Indicator wakeup, either the nRI2 event can be enabled via
bit 1 in the PME_EN1 register or the GP50 PME event can be enabled via bit 0 in the
PME_EN5 register.
If CIR wakeup is to be used with this pin, enable CIR via bit 0 in the PME_EN1
register, do not enable the GP52 PME event via bit 2 in the PME_EN5 register.
In order to use the P12, P16 and P17 functions, the corresponding GPIO must be
programmed for output, non-invert, and push-pull output type.
REG OFFSET
(R/W)
(R/W)
(R/W)
60-7F
(hex)
(R)
5D
5E
5F
DATASHEET
Bit 7 of the FDD Mode Register will also affect the pin if the
LED1
Bit[1:0] LED1 Control
00=off
01=blink at 1Hz rate with a 50% duty cycle (0.5 sec on, 0.5
sec off)
10=Blink at ½ HZ rate with a 25% duty cycle (0.5 sec on, 1.5
sec off)
11=on
Bits[7:2] Reserved
LED2
Bit[1:0] LED2 Control
00=off
01=blink at 1Hz rate with a 50% duty cycle (0.5 sec on, 0.5
sec off)
10=Blink at ½ HZ rate with a 25% duty cycle (0.5 sec on, 1.5
sec off)
11=on
Bits[7:2] Reserved
Keyboard Scan Code
Bit[0] LSB of Scan Code
Bit[7] MSB of Scan Code
Reserved – reads return 0
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DESCRIPTION
Rev. 04-17-07