LPC47B272-MS SMSC, LPC47B272-MS Datasheet - Page 119

• Manufacturer Part Number: LPC47B272-MS
• Description: IC CTRLR SUPER I/O LPC 100-QFP
• Manufacturer: SMSC

Specifications of LPC47B272-MS

• Controller Type: I/O Controller
• Interface: LPC
• Voltage - Supply: 3.3V
• Current - Supply: 15mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 638-1019

The LPC47B27x implements fan speed control outputs and fan tachometer inputs. The implementation
of these features are described in the sections below.
Fan Speed Control
The fan speed control for the LPC47B27x is implemented as pulse width modulators with fan clock
speed selection.
Pins 54 and 55 are the fan speed control outputs, FAN2 and FAN1, respectively, muxed with GPIOs.
These fan control pins come up as outputs and are low following a VCC POR and Hard Reset. These
pins may not be used for wakeup events under VTR power (VCC=0).
The configuration registers are defined in the “Runtime Registers” section.
Fan Speed Control Summary
The following table illustrates the different modes for the fans.
Note 1. This is FANx Register Bit 0
Note 2. This is Fan Control Register Bit 2 or 3
Note 3. This is Fan Control Register Bit 0 or 1
Note 4. This is FANx Register Bit 7
FANx Registers
The FAN1 and FAN2 Registers are located at 0x56 and 0x57 from base I/O in Logical Device A. The
bits are defined below. See the register description in the Runtime Registers section.
Fan x Clock Select Bit, D7
The Fan x Clock Select bit in the FANx registers is used with the Fan x Clock Source Select and the
Fan x Clock Multiplier bits in the Fan Control register to determine the fan speed F
above.
Duty Cycle Control for Fan x, Bits D6 – D1
The Duty Cycle Control (DCC) bits determine the fan duty cycle. The LPC47B27x has ≈ 1.56% duty
cycle resolution.
When DCC = “000000” (min. value), F
almost always high; i.e., high for 63/64
Generally, the F
SMSC LPC47B27x
(Note 1)
Control
Clock
FANx
Bit
0
0
0
0
0
0
0
0
0
1
Multiplier
OUT
(Note 2)
Clock
FANx
Bit
duty cycle (%) is (DCC ÷ 64) × 100.
X
X
0
0
0
0
1
1
1
1
FAN SPEED CONTROL AND MONITORING
Select Bit
(Note 3)
Source
Clock
FANx
Table 58 – Different Modes for Fan
X
X
0
0
1
1
0
0
1
1
th
OUT
and low for 1/64
DATASHEET
is always low. When DCC is “111111” (max. value), F
Select Bit
(Note 4)
Clock
FANx
X
X
0
1
0
1
0
1
0
1
- 119 -
th
0Hz – LOW
15.625kHz
23.438kHz
40Hz
60Hz
31.25kHz
46.876kHz
80Hz
120Hz
0Hz – HIGH
of the F
F
out
OUT
period.
6-Bit Duty
bits[6:1]
Control
(DCC)
Cycle
1-63
0
-
OUT
. See Table 58
Duty Cycle
(DCC/64)
• 100
Rev. 04-17-07
(%)
-
-
OUT
is