LPC47B272-MS SMSC, LPC47B272-MS Datasheet - Page 71

• Manufacturer Part Number: LPC47B272-MS
• Description: IC CTRLR SUPER I/O LPC 100-QFP
• Manufacturer: SMSC

Specifications of LPC47B272-MS

• Controller Type: I/O Controller
• Interface: LPC
• Voltage - Supply: 3.3V
• Current - Supply: 15mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 638-1019

Bit 6 – MIDI Transmit Busy
Bit 6 MIDI Transmit Busy indicates the send (write) state of the MIDI Data port and Command port
(Table 37).
There are no interrupts associated with MIDI transmit (write) data.
Bits[5:0]
RESERVED (Reserved bits cannot be written and return ‘0’ when read).
Command Port
The Command port is used to transfer MPU-401 commands to the Command Controller.
Command port is write-only (Table 38). See Section “MPU-401 Command Controller” below.
Interrupt
The MPU-401 IRQ is asserted (‘1’) when either MIDI receive data or a command acknowledge byte is
available to the host in the MIDI Data register (Figure 3). The IRQ is deasserted (‘0’) when the host
reads the MIDI Data port.
NOTE: If, following a host read, data is still available in the Receive FIFO, the IRQ will remain asserted
(‘1’).
The IRQ is enabled when the ‘Activate’ bit in the MPU-401 configuration registers logical device block is
asserted ‘1’. If the Activate bit is deasserted ‘0’, the MPU-401 IRQ cannot be asserted (see Section
“MPU-401 Configuration Registers”).
The MPU-401 IRQ is not affected by MIDI write data, transmit-related functions or Receiver Line Status
interrupts.
The factory default Sound Blaster 16 MPU-401 IRQ is 5.
NOTE
NOTE
SMSC LPC47B27x
TYPE
NAME
MIDI RX CLOCK
DATA READY
1
2
DATA READY represents the Data Ready bit B0 in the UART Line Status Register.
nREAD represents host read operations from the MIDI Data register.
MIDI_IN
nREAD
MPU-401 I/O BASE ADDRESS+1
D7
W
COMMAND REGISTER
IRQ
4
1
3
2
D6
W
MIDI RX DATA BYTE N
STATUS PORT
D6
0
1
TABLE 37 - MIDI TRANSMIT BUSY STATUS BIT
D5
W
TABLE 38 – MPU-401 COMMAND PORT
FIGURE 3 - MPU-401 INTERRUPT
D4
W
DATASHEET
DESCRIPTION
The MPU-401 interface is ready to accept a
data/command byte from the host.
The MPU-401 interface is NOT ready to
accept a data/command byte from the host.
D3
W
MIDI RX DATA BYTE N+1
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D2
W
D1
W
D0
W
DEFAULT
n/a
NOTE: IRQ remains asserted
until read FIFO is empty
Rev. 04-17-07
The