LPC47B272-MS SMSC, LPC47B272-MS Datasheet - Page 133

• Manufacturer Part Number: LPC47B272-MS
• Description: IC CTRLR SUPER I/O LPC 100-QFP
• Manufacturer: SMSC

Specifications of LPC47B272-MS

• Controller Type: I/O Controller
• Interface: LPC
• Voltage - Supply: 3.3V
• Current - Supply: 15mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 638-1019

SMSC LPC47B27x
PME_EN4
Default = 0x00
PME_EN5
Default = 0x00
on VTR POR
N/A
SMI_STS1
Default = 0x02
on VTR POR
Bit 1 is set to ‘1’ on
VCC POR, VTR
POR, hard reset and
soft reset
on VTR POR
NAME
REG OFFSET
(R/W)
(R/W)
(R/W)
(hex)
(R)
0D
0E
0F
10
DATASHEET
PME Wake Enable Register 4
This register is used to enable individual LPC47B27x PME
wake sources onto the nIO_PME wake bus.
When the PME Wake Enable register bit for a wake source
is active (“1”), if the source asserts a wake event so that
the associated status bit is “1” and the PME_En bit is “1”,
the source will assert the nIO_PME signal.
When the PME Wake Enable register bit for a wake source
is inactive (“0”), the PME Wake Status register will indicate
the state of the wake source but will not assert the
nIO_PME signal.
Bit[0] GP30
Bit[1] GP31
Bit[2] GP32
Bit[3] GP33
Bit[4] GP41
Bit[5] GP43
Bit[6] GP60
Bit[7] GP61
The PME Wake Enable register is not affected by Vcc
POR, SOFT RESET or HARD RESET.
PME Wake Enable Register 5
This register is used to enable individual LPC47B27x PME
wake sources onto the nIO_PME wake bus.
When the PME Wake Enable register bit for a wake source
is active (“1”), if the source asserts a wake event so that
the associated status bit is “1” and the PME_En bit is “1”,
the source will assert the nIO_PME signal.
When the PME Wake Enable register bit for a wake source
is inactive (“0”), the PME Wake Status register will indicate
the state of the wake source but will not assert the
nIO_PME signal.
Bit[0] GP50
Bit[1] GP51
Bit[2] GP52
Bit[3] GP53
Bit[4] GP54
Bit[5] GP55
Bit[6] GP56
Bit[7] GP57
The PME Wake Enable register is not affected by Vcc
POR, SOFT RESET or HARD RESET.
Reserved – reads return 0
SMI Status Register 1
This register is used to read the status of the SMI inputs.
The following bits must be cleared at their source.
Bit[0] Reserved
Bit[1] PINT. The parallel port interrupt defaults to ‘1’ when
the parallel port activate bit is cleared. When the parallel
port is activated, PINT follows the nACK input.
Bit[2] U2INT
Bit[3] U1INT
Bit[4] FINT
Bit[5] MPU-401 INT
Bit[6] Reserved
Bit[7] WDT
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DESCRIPTION
Rev. 04-17-07