LPC47B272-MS SMSC, LPC47B272-MS Datasheet - Page 18

• Manufacturer Part Number: LPC47B272-MS
• Description: IC CTRLR SUPER I/O LPC 100-QFP
• Manufacturer: SMSC

Specifications of LPC47B272-MS

• Controller Type: I/O Controller
• Interface: LPC
• Voltage - Supply: 3.3V
• Current - Supply: 15mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 638-1019

SUPER I/O REGISTERS
The address map, shown below in Table 1, shows the addresses of the different blocks of the Super I/O immediately
after power up. The base addresses of the FDC, serial and parallel ports, PME register block, Game port and
configuration register block can be moved via the configuration registers. Some addresses are used to access more
than one register.
HOST PROCESSOR INTERFACE (LPC)
The host processor communicates with the LPC47B27x through a series of read/write registers via the LPC interface.
The port addresses for these registers are shown in Table 1. Register access is accomplished through I/O cycles or
DMA transfers. All registers are 8 bits wide.
LPC INTERFACE
The following sub-sections specify the implementation of the LPC bus.
LPC Interface Signal Definition
The signals required for the LPC bus interface are described in the table below. LPC bus signals use PCI 33MHz
electrical signal characteristics.
Note: The nCLKRUN signal is not implemented in this part.
SMSC LPC47B27x
LAD[3:0]
nLFRAME
nPCI_RESET
nLDRQ
nIO_PME
nLPCPD
SER_IRQ
PCI_CLK
SIGNAL NAME
Note 1: Refer to the configuration register descriptions for setting the base address.
Base+(0-5) and +(7)
Base+(0-7)
Base1+(0-7)
Base2+(0-7)
Base+(0-3)
Base+(0-7)
Base+(0-3), +(400-402)
Base+(0-7), +(400-402)
60, 64
Base + 0
Base + (0-5F)
Base + (0-1)
Base + (0-1)
I/O
Input
Input
Output
OD
Input
I/O
Input
TYPE
ADDRESS
LPC address/data bus. Multiplexed command, address and data bus.
Frame signal. Indicates start of new cycle and termination of broken
cycle
PCI Reset. Used as LPC Interface Reset.
Encoded DMA/Bus Master request for the LPC interface.
Power Mgt Event signal. Allows the LPC47B27x to request wakeup.
Powerdown Signal. Indicates that the LPC47B27x should prepare for
power to be shut on the LPC interface.
Serial IRQ.
PCI Clock.
Table 1 - Super I/O Block Addresses
FUNCTIONAL DESCRIPTION
DATASHEET
Floppy Disk
Serial Port Com 1
Serial Port Com 2
Parallel Port
SPP
EPP
ECP
ECP+EPP+SPP
KYBD
Game Port
Runtime Registers
MPU-401
Configuration
BLOCK NAME
- 18 -
DESCRIPTION
LOGICAL
DEVICE
A
B
0
4
5
3
7
9
IR Support
Consumer IR
Rev. 04-17-07
NOTES