LPC47B272-MS SMSC, LPC47B272-MS Datasheet - Page 131

• Manufacturer Part Number: LPC47B272-MS
• Description: IC CTRLR SUPER I/O LPC 100-QFP
• Manufacturer: SMSC

Specifications of LPC47B272-MS

• Controller Type: I/O Controller
• Interface: LPC
• Voltage - Supply: 3.3V
• Current - Supply: 15mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 638-1019

SMSC LPC47B27x
PME_STS4
Default = 0x00
(Note 7)
PME_STS5
Default = 0x00
(Note 7)
N/A
PME_EN1
Default = 0x00
on VTR POR
on VTR POR
on VTR POR
NAME
REG OFFSET
(R/W)
(R/W)
(R/W)
(hex)
(R)
07
08
09
0A
DATASHEET
PME Wake Status Register 4
This register indicates the state of the individual PME wake
sources, independent of the individual source enables or
the PME_En bit.
If the wake source has asserted a wake event, the
associated PME Wake Status bit will be a “1”.
Bit[0] GP30
Bit[1] GP31
Bit[2] GP32
Bit[3] GP33
Bit[4] GP41
Bit[5] GP43
Bit[6] GP60
Bit[7] GP61
The PME Wake Status register is not affected by Vcc
POR, SOFT RESET or HARD RESET.
Writing a “1” to Bit[7:0] will clear it. Writing a “0” to any bit
in PME Wake Status Register has no effect.
PME Wake Status Register 5
This register indicates the state of the individual PME wake
sources, independent of the individual source enables or
the PME_En bit.
If the wake source has asserted a wake event, the
associated PME Wake Status bit will be a “1”.
Bit[0] GP50
Bit[1] GP51
Bit[2] GP52
Bit[3] GP53 (Note 8)
Bit[4] GP54
Bit[5] GP55
Bit[6] GP56
Bit[7] GP57
The PME Wake Status register is not affected by Vcc
POR, SOFT RESET or HARD RESET.
Writing a “1” to Bit[7:0] will clear it. Writing a “0” to any bit
in PME Wake Status Register has no effect.
Reserved – reads return 0
PME Wake Enable Register 1
This register is used to enable individual LPC47B27x PME
wake sources onto the nIO_PME wake bus.
When the PME Wake Enable register bit for a wake source
is active (“1”), if the source asserts a wake event so that
the associated status bit is “1” and the PME_En bit is “1”,
the source will assert the nIO_PME signal.
When the PME Wake Enable register bit for a wake source
is inactive (“0”), the PME Wake Status register will indicate
the state of the wake source but will not assert the
nIO_PME signal.
Bit[0] CIR
Bit[1] RI2
Bit[2] RI1
Bit[3] KBD
Bit[4] MOUSE
Bit[5] SPEKEY (Wake on specific key)
Bit[6] FAN_TACH1
Bit[7] FAN_TACH2
The PME Wake Enable register is not affected by Vcc
POR, SOFT RESET or HARD RESET.
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DESCRIPTION
Rev. 04-17-07