LPC47B272-MS SMSC, LPC47B272-MS Datasheet - Page 95

• Manufacturer Part Number: LPC47B272-MS
• Description: IC CTRLR SUPER I/O LPC 100-QFP
• Manufacturer: SMSC

Specifications of LPC47B272-MS

• Controller Type: I/O Controller
• Interface: LPC
• Voltage - Supply: 3.3V
• Current - Supply: 15mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 638-1019

UART Power Management
Direct power management is controlled by CR22. Refer to CR22 for more information.
Auto Power Management is enabled by CR23-B4 and B5. When set, these bits allow the following auto
power management operations:
1.
2.
Note:
Exit Auto Powerdown
The transmitter exits powerdown on a write to the XMIT buffer. The receiver exits auto powerdown when
RXDx changes state.
MPU-401 Power Management
Direct power management is controlled by CR22. Refer to CR22 for more information.
Auto Power Management is enabled by CR23-B6. When set, this bit allows the following auto power
management operations:
1.
2.
Exit Auto Powerdown
The transmitter exits powerdown on a write to the XMIT buffer. The receiver exits auto powerdown when
MIDI_IN changes state.
Parallel Port
Direct power management is controlled by CR22. Refer to CR22 for more information.
Auto Power Management is enabled by CR23-B3. When set, this bit allows the ECP or EPP logical
parallel port blocks to be placed into powerdown when not being used.
The EPP logic is in powerdown under any of the following conditions:
1.
2.
The ECP logic is in powerdown under any of the following conditions:
SMSC LPC47B27x
The transmitter enters auto powerdown when the transmit buffer and shift register are empty.
The receiver enters powerdown when the following conditions are all met:
A.
B.
The transmitter enters auto powerdown when the transmit buffer and shift register are empty.
The receiver enters powerdown when the following conditions are all met:
A.
B.
EPP is not enabled in the configuration registers.
EPP is not selected through ecr while in ECP mode.
Receive FIFO is empty
The receiver is waiting for a start bit.
While in powerdown the Ring Indicator interrupt is still valid and transitions when the RI input
changes.
Receive FIFO is empty
The receiver is waiting for a start bit.
DRVDEN[0:1]
nDSKCHG
FDD PINS
nWGATE
nWDATA
nHDSEL
nINDEX
nMTR0
nSTEP
nTRK0
nDS0
nDIR
DATASHEET
OUTPUT PINS
STATE IN AUTO POWERDOWN
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Tristated
Tristated
Tristated
Tristated
Active
Active
Active
Active
Input
Input
Input
Rev. 04-17-07