LPC47B272-MS SMSC, LPC47B272-MS Datasheet - Page 13

• Manufacturer Part Number: LPC47B272-MS
• Description: IC CTRLR SUPER I/O LPC 100-QFP
• Manufacturer: SMSC

Specifications of LPC47B272-MS

• Controller Type: I/O Controller
• Interface: LPC
• Voltage - Supply: 3.3V
• Current - Supply: 15mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 638-1019

REFERENCE DOCUMENTS
1.
2.
3.
4.
5.
6.
7.
3 VOLT OPERATION / 5 VOLT TOLERANCE
The LPC47B27x is a 3.3 Volt part. It is intended solely for 3.3V applications. Non-LPC bus pins are 5V tolerant; that
is, the input voltage is 5.5V max, and the I/O buffer output pads are backdrive protected.
The LPC interface pins are 3.3 V only. These signals meet PCI DC specifications for 3.3V signaling. These pins are:
•
•
•
•
The input voltage for all other pins is 5.5V max. These pins include all non-LPC Bus pins and the following pins:
•
•
•
•
SMSC LPC47B27x
LPC Bus
Signals
SMSC Consumer Infrared Communications Controller (CIrCC) V1.X
IEEE 1284 Extended Capabilities Port Protocol and ISA Standard, Rev. 1.14, July 14, 1993.
Hardware Description of the 8042, Intel 8 bit Embedded Controller Handbook.
PCI Bus Power Management Interface Specification, Rev. 1.0, Draft, March 18, 1997.
Low Pin Count (LPC) Interface Specification, Revision 1.0, September 29, 1997, Intel Document.
SMSC Application Note, AN 8-8: Using the Enhanced Keyboard and Mouse Wakeup Feature in SMSC Super I/O
Parts.
SMSC Application Note, AN 9-3: Application Considerations When Using the Powerdown Feature of SMSC
Floppy Disk Controllers.
LAD[3:0]
nLFRAME
nLDRQ
nLPCPD
nPCI_RESET
PCI_CLK
SER_IRQ
nIO_PME
SER_IRQ
PCI_CLK
V
INTERFACE
TR
LPC BUS
SERIAL
IRQ
Vcc Vss
nIO_SMI
32KHz
CLK32
SMI
CLOCK
GEN
CLOCKI
14MHz
nIO_PME
PME
nDSKCHG
nWRPRT
nWGATE
FIGURE 1 – LPC47B27x BLOCK DIAGRAM
WDT
BLOCK
nINDEX
nTRK0
ACPI
ADDRESS BUS
PROPRIETARY
CONTROLLER
COMPATIBLE
FLOPPYDISK
VERTICAL
DENSEL
SMSC
nHDSEL
82077
CORE
nSTEP
nDIR
Game Port Signals*
CONFIGURATION
CONTROL BUS
REGISTERS
Game Port
DRVDEN0
DRVDEN1
DATA BUS
nMTR0
nDS0
(1-Dual)
WCLOCK
RCLOCK
WDATA
RDATA
...
nWDATA nRDATA
*
BLOCK DIAGRAM
DATASHEET
SEPARATOR
WITH WRITE
PENSATION
PRECOM-
DIGITAL
DATA
FAN1*
FAN2*
Control
Fan
- 13 -
FAN_TACH1*
FAN_TACH2*
*
Denotes Multifunction Pins
MULTI-MODE
PORT 2 WITH
COMPATIBLE
COMPATIBLE
PORT/FDC
PARALLEL
GENERAL
PURPOSE
INFRARED
SERIAL
PORT 1
16C550
SERIAL
MPU-401
16C550
SERIAL
MUX
PORT
8042
I/O
nDSR1, nDCD1, nRI1, nDTR1
IRRX, IRTX
TXD2(IRTX), nCTS2, nRTS2
RXD2(IRRX)
nDSR2, nDCD2, nRI2, nDTR2
BUSY, SLCT, PE,
nERROR, nACK
nSTB, nSLCTIN,
nINIT , nALF
TXD1, nCTS1, nRTS1
RXD1
KCLK
KDATA
MCLK
MDATA
GATEA20, KRESET
PD0-7
GP1[0:7]*
GP2[0:2,4:7]*
GP3[0:7]*, GP4[0:3]*
GP5[0:7]*, GP6[0:1]*
MIDI_IN
MIDI_OUT
*
Rev. 04-17-07
*
*