LPC47B272-MS SMSC, LPC47B272-MS Datasheet - Page 94

• Manufacturer Part Number: LPC47B272-MS
• Description: IC CTRLR SUPER I/O LPC 100-QFP
• Manufacturer: SMSC

Specifications of LPC47B272-MS

• Controller Type: I/O Controller
• Interface: LPC
• Voltage - Supply: 3.3V
• Current - Supply: 15mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 638-1019

retaining the data and subsequently reflecting it when the part awakens. Accessing the part during
powerdown may cause an increase in the power consumption by the part. The part will revert back to its
low power mode when the access has been completed.
Pin Behavior
The LPC47B27x is specifically designed for systems in which power conservation is a primary concern.
This makes the behavior of the pins during powerdown very important.
The pins of the LPC47B27x can be divided into two major categories: system interface and floppy disk
drive interface. The floppy disk drive pins are disabled so that no power will be drawn through the part as
a result of any voltage applied to the pin within the part's power supply range. Most of the system interface
pins are left active to monitor system accesses that may wake up the part.
Note 1: Writing to the DOR or DSR does not wake up the part, however, writing any of the motor enable
System Interface Pins
Table 49 gives the state of the interface pins in the powerdown state. Pins unaffected by the powerdown
are labeled "Unchanged".
FDD Interface Pins
All pins in the FDD interface which can be connected directly to the floppy disk drive itself are either
DISABLED or TRISTATED.
Pins used for local logic control or part programming are unaffected. Table 50 depicts the state of the
floppy disk drive interface pins in the powerdown state.
SMSC LPC47B27x
bits or doing a software reset (via DOR or DSR reset bits) will wake up the part.
BASE + ADDRESS
Table 50 - State of Floppy Disk Drive Interface Pins in Powerdown
00H
01H
02H
03H
04H
06H
07H
07H
04H
05H
SYSTEM PINS
Table 49 – State of System Pins in Auto Powerdown
Access to these registers DOES NOT wake up the part
nPCI_RESET
nLFRAME
SER_IRQ
nWRTPRT
PCI_CLK
FDD PINS
LAD[3:0]
nLPCPD
Table 48 - PC/AT and PS/2 Available Registers
nRDATA
nLDRQ
Access to these registers wakes up the part
DOR (1)
DSR (1)
PC-AT
MSR
CCR
Data
AVAILABLE REGISTERS
DIR
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DATASHEET
INPUT PINS
STATE IN AUTO POWERDOWN
PS/2 (MODEL 30)
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DOR (1)
DSR (1)
STATE IN AUTO POWERDOWN
CCR
MSR
SRA
SRB
Data
DIR
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Input
Input
Unchanged
Unchanged
Unchanged
Unchanged
Unchanged
Unchanged
Unchanged
ACCESS PERMITTED
R/W
R/W
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W
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W
R
R
R
R
Rev. 04-17-07