LPC47B272-MS SMSC, LPC47B272-MS Datasheet - Page 98

• Manufacturer Part Number: LPC47B272-MS
• Description: IC CTRLR SUPER I/O LPC 100-QFP
• Manufacturer: SMSC

Specifications of LPC47B272-MS

• Controller Type: I/O Controller
• Interface: LPC
• Voltage - Supply: 3.3V
• Current - Supply: 15mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 638-1019

The SMI is enabled onto the SMI frame of the Serial IRQ via bit 6 of SMI Enable Register 2 and onto
the SMI pin via bit 7 of the SMI Enable Register 2.
Stop Cycle Control
Once all IRQ/Data Frames have completed the Host Controller will terminate SER_IRQ activity by
initiating a Stop Frame. Only the Host Controller can initiate the Stop Frame. A Stop Frame is
indicated when the SER_IRQ is low for two or three clocks. If the Stop Frame’s low time is two clocks
then the next SER_IRQ Cycle’s sampled mode is the Quiet mode; and any SER_IRQ device may
initiate a Start Frame in the second clock or more after the rising edge of the Stop Frame’s pulse. If the
Stop Frame’s low time is three clocks then the next SER_IRQ Cycle’s sampled mode is the Continuos
mode; and only the Host Controller may initiate a Start Frame in the second clock or more after the
rising edge of the Stop Frame’s pulse.
Latency
Latency for IRQ/Data updates over the SER_IRQ bus in bridge-less systems with the minimum Host
supported IRQ/Data Frames of 17, will range up to 96 clocks (3.84 µ S with a 25MHz PCI Bus or 2.88uS
with a 33MHz PCI Bus). If one or more PCI to PCI Bridge is added to a system, the latency for
IRQ/Data updates from the secondary or tertiary buses will be a few clocks longer for synchronous
buses, and approximately double for asynchronous buses.
EOI/ISR Read Latency
Any serialized IRQ scheme has a potential implementation issue related to IRQ latency. IRQ latency
could cause an EOI or ISR Read to precede an IRQ transition that it should have followed. This could
cause a system fault. The host interrupt controller is responsible for ensuring that these latency issues
are mitigated. The recommended solution is to delay EOIs and ISR Reads to the interrupt controller by
the same amount as the SER_IRQ Cycle latency in order to ensure that these events do not occur out
of order.
AC/DC Specification Issue
All SER_IRQ agents must drive / sample SER_IRQ synchronously related to the rising edge of PCI bus
clock. The SER_IRQ pin uses the electrical specification of PCI bus. Electrical parameters will follow
PCI spec. section 4, sustained tri-state.
Reset and Initialization
The SER_IRQ bus uses nPCI_RESET as its reset signal. The SER_IRQ pin is tri-stated by all agents
while nPCI_RESET is active. With reset, SER_IRQ Slaves are put into the (continuous) IDLE mode.
The Host Controller is responsible for starting the initial SER_IRQ Cycle to collect system’s IRQ/Data
default values. The system then follows with the Continuous/Quiet mode protocol (Stop Frame pulse
width) for subsequent SER_IRQ Cycles. It is Host Controller’s responsibility to provide the default
values to 8259’s and other system logic before the first SER_IRQ Cycle is performed. For SER_IRQ
system suspend, insertion, or removal application, the Host controller should be programmed into
Continuous (IDLE) mode first. This is to guarantee SER_IRQ bus is in IDLE state before the system
configuration changes.
SMSC LPC47B27x
- 98 -
Rev. 04-17-07
DATASHEET