LPC47B272-MS SMSC, LPC47B272-MS Datasheet - Page 135
LPC47B272-MS
Manufacturer Part Number
LPC47B272-MS
Description
IC CTRLR SUPER I/O LPC 100-QFP
Manufacturer
SMSC
Datasheet
1.LPC47B272-MS.pdf
(195 pages)
Specifications of LPC47B272-MS
Controller Type
I/O Controller
Interface
LPC
Voltage - Supply
3.3V
Current - Supply
15mA
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
100-QFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
638-1019
Available stocks
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Quantity
Price
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Part Number:
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SMSC LPC47B27x
SMI_EN2
Default = 0x00
SMI_EN3
Default = 0x00
SMI_EN4
Default = 0x00
SMI_EN5
Default = 0x00
N/A
on VTR POR
on VTR POR
on VTR POR
on VTR POR
NAME
REG OFFSET
(R/W)
(R/W)
(R/W)
(R/W)
(hex)
(R)
1A
1B
17
18
19
DATASHEET
SMI Enable Register 2
This register is used to enable the different interrupt sources
onto the group nSMI output, and the group nSMI output onto
the nIO_SMI GPI/O pin, the serial IRQ stream or into the
PME Logic.
Unless otherwise noted,
1=Enable
0=Disable
Bit[0] EN_MINT
Bit[1] EN_KINT
Bit[2] EN_IRINT
Bit[3] Reserved
Bit[4] EN_P12
Bit[5] EN_SMI_PME (Enable group SMI into PME logic)
Bit[6] EN_SMI_S (Enable group SMI onto serial IRQ)
Bit[7] EN_SMI (Enable group SMI onto nIO_SMI pin)
SMI Enable Register 3
This register is used to enable the different interrupt sources
onto the group nSMI output.
1=Enable
0=Disable
Bit[0] GP20
Bit[1] GP21
Bit[2] GP22
Bit[3] Reserved
Bit[4] GP24
Bit[5] GP25
Bit[6] GP26
Bit[7] GP60
SMI Enable Register 4
This register is used to enable the different interrupt sources
onto the group nSMI output.
1=Enable
0=Disable
Bit[0] GP30
Bit[1] GP31
Bit[2] GP32
Bit[3] GP33
Bit[4] GP41
Bit[5] GP42
Bit[6] GP43
Bit[7] GP61
SMI Enable Register 5
This register is used to enable the different interrupt sources
onto the group nSMI output.
1=Enable
0=Disable
Bit[0] GP54
Bit[1] GP55
Bit[2] GP56
Bit[3] GP57
Bit[4] Reserved
Bit[5] Reserved
Bit[6] FAN_TACH1
Bit[7] FAN_TACH2
Reserved – reads return 0
- 135 -
DESCRIPTION
Rev. 04-17-07
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