M69030 Asiliant Technologies, M69030 Datasheet - Page 113

• Manufacturer Part Number: M69030
• Manufacturer: Asiliant Technologies

Specifications of M69030

• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Operating Temperature (max): 70C
• Rad Hardened: No
• Lead Free Status / Rohs Status: Supplier Unconfirmed

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Vertical Blanking Start Bit 8
Vertical Sync Start Bit 8
69030 Databook
The vertical blanking start is a 10-bit or 12-bit value that specifies the beginning of the
vertical blanking period relative to the beginning of the active display area.
In standard VGA modes, where bit 0 of the I/O Control Register (XR09) is set to 0, the
vertical blanking start is specified with a 10-bit value. The 8 least significant bits of the
vertical blanking start are supplied by bits 7-0 of the Vertical Blanking Start Register
(CR15), and the most and second-most significant bits are supplied by bit 5 of the
Maximum Scanline Register (CR09) and bit 3 of this register (CR07), respectively.
In extended modes, where bit 0 of the I/O Control Register (XR09) is set to 1, the vertical
blanking start is specified with a 12-bit value. The 8 least significant bits of the vertical
blanking start are supplied by bits 7-0 of the Vertical Blanking Start Register (CR15), and
the 4 most significant bits are supplied by bits 3-0 of the Extended Vertical Blanking Start
Register (CR33). In extended modes, neither bit 3 of CR07 nor bit 5 of the Maximum
Scanline Register (CR09) are used.
This 10-bit or 12-bit value should be programmed to be equal to the number of scanlines
from the beginning of the active display area to the beginning of the blanking period. Since
the active display area always starts on the 0th scanline, this number should be equal to
the number of the scanline on which the vertical blanking period begins.
The vertical sync start is a 10-bit or 12-bit value that specifies the beginning of the vertical
sync pulse relative to the beginning of the active display area.
In standard VGA modes, where bit 0 of the I/O Control Register (XR09) is set to 0, the
vertical sync start is specified with a 10-bit value. The 8 least significant bits of the vertical
sync start are supplied by bits 7-0 of the Vertical Sync Start Register (CR10), and the most
and second-most significant bits are supplied by bit 7 and bit 2 of this register (CR07),
respectively.
In extended modes, where bit 0 of the I/O Control Register (XR09) is set to 1, the vertical
display end is specified with a 12-bit value. The 8 least significant bits of the vertical display
are supplied by bits 7-0 of the Vertical Sync Start Register (CR10), and the 4 most
significant bits are supplied by bits 3-0 of the Extended Vertical Sync Start Register (CR32)
register. In extended modes, neither bit 7 nor bit 2 of this register (CR07) are used.
This 10-bit or 12-bit value should be programmed to be equal to the number of scanlines
from the beginning of the active display area to the start of the vertical sync pulse. Since
the active display area always starts on the 0th scanline, this number should be equal to
the number of the scanline on which the vertical sync pulse begins.
CRT Controller Registers
Revision 1.3 11/24/99
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