M69030 Asiliant Technologies, M69030 Datasheet - Page 79

• Manufacturer Part Number: M69030
• Manufacturer: Asiliant Technologies

Specifications of M69030

• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Operating Temperature (max): 70C
• Rad Hardened: No
• Lead Free Status / Rohs Status: Supplier Unconfirmed

DEVSTAT
read/write at PCI configuration offset 06h
byte or word accessible
accessible only via PCI configuration cycles
Important: Read accesses to this register behave normally. Writes, however, behave differently in that
bits can be reset to 0, but not set to 1. A bit in this register is reset to 0 whenever it is written with the value
of 1. Bits written with a value of 0 are entirely unaffected.
15
14
13
12
11
`efmp
Parity
Error
Det
15
(0)
System

Signal
Error
Detected Parity Error
Signaled System Error
Received Master Abort
Received Target Abort
Signaled Target Abort
69030 Databook
(0)
14
Master
Rcvd
Abort
(0)
13
0: No address or data parity error detected.
1: An address or data parity error was detected.
Note: This bit is set in response to a parity error regardless of the settings of either bit 6
(Parity Error Response bit) and 8 (SERR# Enable) of the Device Control Register
(DEVCTL).
0: SERR# has not been asserted.
1: SERR# has been asserted.
Note: Both bits 6 (Parity Error Response bit) and 8 (SERR# Enable) of the Device Control
Register (DEVCTL) must both be set to 1 to enable the use of SERR# and the setting of
this bit to 1 in response to an address parity error.
This bit applies only to PCI Bus masters. Since this graphics controller never functions as
a PCI Bus master, this bit always returns a value of 0 when read.
This bit applies only to PCI Bus masters. Since this graphics controller never functions as
a PCI Bus master, this bit always returns a value of 0 when read.
0: A target abort was not generated.
1: A target abort was generated.
A target abort can be generated by this graphics controller on I/O cycles with non-adjacent
active byte enables.
Target
Abort
Rcvd
Device Status Register
(0)
12
Target
Signal
Abort
(0)
11
10
DEVSEL#
Timing
(01)
PCI Configuration Registers
9
Parity
Data
Error
(0)
8
Back-
Back
Fast
(1)
7
UDF
(0)
6
MHz
66
(1)
5
4
3
Revision 1.3 11/24/99
Reserved
(0:0000)
2
1
0
7-5