M69030 Asiliant Technologies, M69030 Datasheet - Page 30

• Manufacturer Part Number: M69030
• Manufacturer: Asiliant Technologies

Specifications of M69030

• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Operating Temperature (max): 70C
• Rad Hardened: No
• Lead Free Status / Rohs Status: Supplier Unconfirmed

2-6
B69030 and M69030 PCI/AGP Bus Interface (continued)
Note:
driven high for one clock before released, and are not driven for at least one cycle after being released by
the previous device. A pull-up provided by the bus controller is used to maintain an inactive level between
transactions.
`efmp
BGA
Pin
A4
L4
L2
L3

mBGA
S/TS stands for “Sustained Tri-state”. These signals are driven by only one device at a time, are
69030 Databook
Pin
B5
J5
J3
J4
Pin Name
DEVSEL#
PERR#
SERR#
INT#
Type
S/TS
S/TS
OD
OD
Active Powered
Low
Low
Low
Low
IOVCC
& GND
IOVCC
& GND
IOVCC
& GND
IOVCC
& GND
Pin Descriptions
Device Select. Indicates the current target has decoded its
address as the target of the current access
Parity Error. This signal reports data parity errors (except
for Special Cycles where SERR# is used). The PERR# pin
is Sustained Tri-state. The receiving agent will drive
PERR# active two clocks after detecting a data parity error.
PERR# will be driven high for one clock before being tri-
stated as with all sustained tri-state signals. PERR# will not
report status until the chip has claimed the access by
asserting DEVSEL# and completing the data phase.
System Error. Used to report system errors where the result
will be catastrophic (address parity error, data parity errors
for Special Cycle commands, etc.). This output is actively
driven for a single PCI/AGP clock cycle synchronous to
BCLK and meets the same setup and hold time
requirements as all other bused signals. SERR# is not
driven high by the chip after being asserted, but is pulled
high only by a weak pull-up provided by the system. Thus,
SERR# on the PCI/AGP bus may take two or three clock
periods to fully return to an inactive state.
Interrupt request pin.
Description
Revision 1.3 11/24/99