M69030 Asiliant Technologies, M69030 Datasheet - Page 163
M69030
Manufacturer Part Number
M69030
Description
Manufacturer
Asiliant Technologies
Datasheet
1.M69030.pdf
(387 pages)
Specifications of M69030
Operating Temperature (min)
0C
Operating Temperature Classification
Commercial
Operating Temperature (max)
70C
Rad Hardened
No
Lead Free Status / Rohs Status
Supplier Unconfirmed
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`efmp
Odd/Even Mode
69030 Databook
This alternating pattern is meant to accommodate the use of the Odd/Even mode of
organizing the 4 memory planes, which is used by standard VGA modes 2h and 3h.
1, x: Four bits of data at a time from parallel bytes in each of the 4 memory planes are
transferred to the palette in a pattern that iterates per byte through memory planes 0
through 3. First the 4 most significant bits of a byte in memory plane 0 are transferred via
the 4 serial output bits, followed by the 4 least significant bits of the same byte. Next, the
same transfers occur from the parallel byte in memory planes 1, 2 and lastly, 3. Each
transfer provides either the upper or lower half of an 8 bit value for the color for each pixel,
making possible a choice of 1 of 256 colors per pixel.
This pattern is meant to accommodate mode 13h, a standard VGA 256-color graphics
mode.
0: Addresses sequentially access data within a bit map. The choice of which map is
accessed is made according to the value of the Plane Mask Register (SR02).
1: The frame buffer is mapped so that address bit 0 is used to select between sets of planes
such that even addresses select memory planes 0 and 2 and odd addresses select memory
planes 1 and 3.
Note: This works in a way that is the inverse of (and is normally set to be the opposite of)
bit 2 of the Memory Mode Register (SR04).
Serial Out 1st Xfer
Bit 3
Bit 2
Bit 1
Bit 0
plane 0
plane 0
plane 0
plane 0
bit 7
bit 6
bit 5
bit 4
plane 0
plane 0
plane 0
plane 0
Graphics Controller Registers
Xfer
bit 3
bit 2
bit 1
bit 0
2nd
plane 1
plane 1
plane 1
plane 1
Xfer
bit 7
bit 6
bit 5
bit 4
3rd
4th Xfer 5th Xfer 6th Xfer 7th Xfer 8th Xfer
plane 1
plane 1
plane 1
plane 1
bit 3
bit 2
bit 1
bit 0
plane 2
plane 2
plane 2
plane 2
bit 7
bit 6
bit 5
bit 4
plane 2
plane 2
plane 2
plane 2
bit 3
bit 2
bit 1
bit 0
plane 3
plane 3
plane 3
plane 3
bit 7
bit 6
bit 5
bit 4
Revision 1.3 11/24/99
plane 3
plane 3
plane 3
plane 3
bit 3
bit 2
bit 1
bit 0
11-7
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